Venice rumors here please!

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dualblade said:
if the tdp is the same, then what's the benefit? i'm building a a64 htpc and am trying to decide whether or not to wait for venice. i don't want to pull the trigger too fast and miss out on something good
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that was kinda the point of my post, the product data seems to be bad.. the tdp should be different.. as should a few other things.
 
Teukka76 said:
Theres something wierd in those CPUs, 3500+ sledgehammer? :confused:

This is what I saw on finnish forum:

That is for code ADA3500DEP4AS

1. Recognized as 130nm NewCastle
2. CBID can't read OPN# or release date (this works with NewCastle/Winchester)
3. As cool as Winchester (28c in bios with stock cooling)
4. CPU-Z:n says cpuz.cvf is corrupted
5. According to reliable source this should be successor of Winchester

:confused: :confused:
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How does the Identifying program work, if it needs to be updated with data re: the new cores I don't know could someone elaborate pls.
 
though i emphasize now that it is a winchester based core, you guys who don't read XS might get a kick out of this
 
jesus christ when will the venice come. I've topped out my 3000+ w/ BH5 the second day I had it

:(

I'm getting new ram in so we'll see. OCZ VX value should be here mid next week :)
 
Teukka76 said:
Theres something wierd in those CPUs, 3500+ sledgehammer? :confused:

This is what I saw on finnish forum:
CBID.PNG

That is for code ADA3500DEP4AS

1. Recognized as 130nm NewCastle
2. CBID can't read OPN# or release date (this works with NewCastle/Winchester)
3. As cool as Winchester (28c in bios with stock cooling)
4. CPU-Z:n says cpuz.cvf is corrupted
5. According to reliable source this should be successor of Winchester

:confused: :confused:
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That isn't a venice....notice the lack of SSE3 instructions....whoever bought that got screwed.
 
haha, i think we've already had a joke about venice the city.

though as a side note, the threads on the turion and 4200+...
those are both based on rev. E (same thing venice will be)
 
San Diego / Venice..

Isn't the San Diego the Opteron Core???

If so wont the memorycontroler require registered RAM?

What have I missed here?
 
it'll also be the FX. i think amd can enable or disable the need for registered ram depending on if they put it in s940 package or not.
 
(cf)Eclipse said:
haha, i think we've already had a joke about venice the city.

though as a side note, the threads on the turion and 4200+...
those are both based on rev. E (same thing venice will be)
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There are clearly two distinct versions of Turion, the 1Mb and 512Kb cache models, though.
 
yup, but they're still based on rev. E :D
(and no, i'll never buy the 512kb version if i don't have to :p)
 
AMD is announcing a revision change for its:

Desktop AMD Athlon(tm) 64 processors from revision D0 to E3 for model numbers 3500+, 3200+ and 3000+ in socket 939.
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_1_UK.pdf

Desktop AMD Athlon(tm) 64 processor 3800+ from revision CG to E3.
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_2_UK.pdf

Desktop AMD Athlon(tm) 64 processor 4000+ from revision CG to E4.
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_3_UK.pdf
 
good call on that ackbar.. i was just about to post it myself :D

now.. this means about another month. hopefully reviewers will get some samples to play with before then, and we can get these concernes about the memory controller and power dissipation sorted out.
also, they had better finally update that damn spec sheet
 
(cf)Eclipse said:
yup, but they're still based on rev. E :D
(and no, i'll never buy the 512kb version if i don't have to :p)
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What do you mean revision E? They're different cores. Why don't you say they're based on the AMD64 architecture while at it?
 
rev E = sSOI 90nm. (afaik)
the only difference that i know of between these 'different' cores is akin to the difference between clawhammer and newcastle: the cache size.
 
They won't do strained soi on all the chips. I'd think only the FX line, if they can maybe high end chips too.
 
are you sure? it wouldn't make sense to have more production lines than necessary, plus strained silicon would be handy to hit higher speeds, so why not put it in all the chips and get as much experience making the stuff as possible?
 
i didn't find out, i'm speculating too, along with some other people..

really, it only makes sense that they go ahead and put sSOI in.. esp if they're giving it a whole new revision letter instead of changing the second part like they did with C0 and CG..
 
Link to forum post and link to inquirer news bit

Looks like Rev E procs will be out on April 4th, along with (possibly) FX-57 and 4200+

AcesHardware said:
[size=-1] Rev E 90nm desktop A64 and A64/FX.

E3 = 512K L2 Rev E desktop
E4 = 1MB L2 Rev E desktop

3000+, 3200+, 3500+, 3800+, 4000+ changing over to Rev E that day.

I suspect the 4200+ and FX-57 will be introduced the same day.
[/size][size=-1] I suspect the 4200+ and FX-57 will be introduced the same day.

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_1_UK.pdf
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_2_UK.pdf
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Rev_change_3_UK.pdf[/size][size=-1]
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Awesomeness...
[/size]
 
very nice info, wonder how long it'll take for prices to come down to current prices and for supply to normalize.
 
supply shouldn't be too bad. all the rev E opterons i've seen have been made back in week 46 or 48, so these things should have been sitting on the shelves for some time now, just waiting for amd to make the move.
 
so.. the E3 will be normal Athlon 64s, and the E4 with the 1 meg cache will be FX's? or will we be seeing normal A64's with 1mb again?
 
i don't know what you mean by 'normal' a64's.. 1mb of cache came first, then 512kb

E3 = 512kb
E4 = 1mb

not all E4's will be fx's though.. they also go into opterons, the 4000+, and the 1mb mobile chips.
 
They wont be out for probably 6 months, so no, pricing is certainly not available.
 
Jason711 said:
the rev E 3000-3500 should be kick ass.
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not necessarily. since winchester's highest model was the 2.2ghz 3500+, it was ok if they didn't really get sorted too much. now there's also all the opterons, 4000+, 3800+, and turion to go with the lower models.
this would imply more strict speed binning, and the best cores will probably go to the mobile line.
 
(cf)Eclipse said:
not necessarily. since winchester's highest model was the 2.2ghz 3500+, it was ok if they didn't really get sorted too much. now there's also all the opterons, 4000+, 3800+, and turion to go with the lower models.
this would imply more strict speed binning, and the best cores will probably go to the mobile line.
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yes especailly with 25W and 35W models being binned. but i guess the amount of chips binned as mobiles would depend on the demand for them and how well they compete with the centrino platform.

however if the tdp is lower we should still get a decent overclock assuming leakage does not increase too much when more voltage is applied.
 
well the way i see it, amd bins in two ways:

by speed. if a chip can't do a certain speed, then obviously is gets put into a model below that speed

by heat output. i've decided that all chips vary a lot on how much power they produce. the mobile chips get the best of these bins. there no other reason as to why an undervolted clawhammer that should be at 72w with 1.4v suddenly is spec'ed at 62w. so my thought here is that if a chip can do a speed, but it over the thermal spec, it gets bumped down until it's within the thermal specs.
 
(cf)Eclipse said:
well the way i see it, amd bins in two ways:

by speed. if a chip can't do a certain speed, then obviously is gets put into a model below that speed

by heat output. i've decided that all chips vary a lot on how much power they produce. the mobile chips get the best of these bins. there no other reason as to why an undervolted clawhammer that should be at 72w with 1.4v suddenly is spec'ed at 62w. so my thought here is that if a chip can do a speed, but it over the thermal spec, it gets bumped down until it's within the thermal specs.
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well, lets hope they all o/c well reguardless... :D
 
Jason711 said:
well, lets hope they all o/c well reguardless... :D
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if you have the cooling and the tdp remains the same I'd assume you could oc it as much as the winnies.
 
DryFire said:
if you have the cooling and the tdp remains the same I'd assume you could oc it as much as the winnies.
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well, when the time comes. i should have water-cooling. i suppose should is the operative word though. *shrug*
 
well winchesters don't really run too hot. and seeing the TDP for the turion line at 1.35v, i think the new revision should run a bit cooler, unless they keep the same TDP for better thermal binning purposes.
 
so it seems like the venice is going to come in mid april instead? or are we still narrowing it down more towards early april? speculation?
 
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