Venice rumors here please!

[(cf)Eclipse]

scali, the way you phrased that, it makes it sound like just by simply moving to a smaller process, performance should jump up

also, amd's 90nm cpu's are cooler than 130nm. tdp went down from 89w to 67. that's a pretty good drop imo

 

[Josh_B]

From xbit labs: "So, we have to conclude that SSE3 instructions (or at least their implementation in the new Athlon 64 processors) are of no practical use."

Wouldn't it be smarter to first figure out if SSE3 instructions are actually _used_ before rejecting them outhand? Maybe this software simply doesn't look for SSE3 in AMD processors?

It's not like it's unheard of...

Also, it's a weird thing to say because they've already shown in an earlier benchmark (patch superpi) that SSE3 _does_ make a difference.

I think you're quite right. Instead of querying the CPU to see what instructions it supports, most commonly applications simply check the CPUID and assume certain functions are enabled/not present/disabled.

 

[Scali]

Woohaa... Are U saying that when running a 64-bited OS the FPU and MMX wont work. Well then obvoisly the SSE 1.2.3. will have more impact. Not that Im about to jump the 64 bit bandwagon yet. (I will when CS shows up better in 64 bit )

That is correct. Well, that is, it won't work in 64 bit applications. The 32 bit legacy mode still supports it ofcourse, even in a 64 bit OS. But 64 bit applications will strictly use SSE/SSE2 instead of FPU/MMX, if all is well.
At least, this is the case in Windows XP 64, because it simply doesn't save the context of the x87/MMX/3DNow! units, so it cannot be used in a multitasking environment.

 

[Scali]

scali, the way you phrased that, it makes it sound like just by simply moving to a smaller process, performance should jump up

That's what historically happened yes, and when it didn't happen for Intel for the first time in history, they got a lot of flack. So now it's only fair to give AMD the same amount of flack, since they 'failed' in exactly the same way. Unless you're biased ofcourse.

 

[dualblade]

That's what historically happened yes, and when it didn't happen for Intel for the first time in history, they got a lot of flack. So now it's only fair to give AMD the same amount of flack, since they 'failed' in exactly the same way. Unless you're biased ofcourse.

i think intel got alot of flack for die shrinking and upping the cache while increasing heat and lowering specific output (ipc). the longer pipeline they've created forces them to ramp up the clockspeed and, fan-boys aside, any educated individual can now see that this is a dead end solution because of extreme heat and leakage issues, and the diminishing returns and increased difficulty of die shrinks. look at all the trouble intel has had going to 90nm, and the time that amd has taken so that they wouldn't face the same trouble.

i don't see how a die shrink in and of itself would increase performance. i thought die shrinks were more of a means to an end, in that the shrink enables higher clock speeds at lower tdp. the reason performance is usually gained is because of accompanying performance increasing elements given to a processor at the time of the core revision(half speed -> full speed cache, doubling of cache, adding of instructions...)

 

[Scali]

i think intel got alot of flack for die shrinking and upping the cache while increasing heat and lowering specific output (ipc). the longer pipeline they've created forces them to ramp up the clockspeed and, fan-boys aside, any educated individual can now see that this is a dead end solution because of extreme heat and leakage issues, and the diminishing returns and increased difficulty of die shrinks.

You forget that Intel also moved from 32 to 64 bit in that same die-shrink. That's probably the main reason for making the pipeline longer. Obviously Intel knows that they have to keep the pipeline as short as possible... But like AMD, Intel had to add a few stages when moving from 32 to 64 bit.
And a considerable amount of the heat is actually caused by the leakage, not by the long pipelines or high clockspeed itself. If you would consider a theoretical P4 with virtually no leakage, instead of the ~25% leakage they have now, then the P4 would be able to scale much higher in clockspeeds and/or get temperatures that would not be too far from the Athlons.
It's just a case of getting the leakage under control... which happens bit by bit. No dead end.

i don't see how a die shrink in and of itself would increase performance. i thought die shrinks were more of a means to an end, in that the shrink enables higher clock speeds at lower tdp.

Exactly, which was my point. That's what happened historically. Obviously the dieshrink itself didn't do anything... But the smaller surface area results in many things, like better yields, lower voltage, temperature etc... which means you can scale up clockspeed 'for free'. But indeed, usually a dieshrink requires a redesign of the core anyway (it's not just a case of taking the 130 nm design and scaling everything down for the 90 nm scale), and while they're redesigning the core for the new process, they add some improvements and/or new features. But most of the gain in clockspeed was historically a result of the dieshrink. Back in the day the pipelines were usually not extended anyway. But everything changed after the PIII era, where you could no longer increase IPC and clockspeed at the same time... which is another story altogether. Short version: AMD focused on IPC, Intel focused on clockspeed. Intel was initially ahead, but being ahead also means you run into problems first.

 

[(cf)Eclipse]

That's what historically happened yes, and when it didn't happen for Intel for the first time in history, they got a lot of flack. So now it's only fair to give AMD the same amount of flack, since they 'failed' in exactly the same way. Unless you're biased ofcourse.

scali.. man. haha, i dunno what to say. i said that simply scaling down the process size will not yeild any performance benefits. you cannot argue that. the reason that intel normally gets more performance out of a smaller process is because they normally double the cache and try to make the core more efficient. this is a change to the core itself, if the northwood was scaled back to .18 microns like the willamette was, but didn't chage the basic core, it would behave exactly the same. only the electrical/thermal characteristics are changed.

with 130nm->90nm, intel made radical changes to the core, planning on the 90nm process doing better than it did. the added pipelines ended up making it less efficient, as i'm sure you know. better branch prediction, sse3, along with some other minor tweaks took up some of the slack, but the fact remains that prescott is less efficient due to the changed architecture, NOT the scaling to 90nm.

then compare to what AMD did: took the 130nm newcastle core, shrunk it to 90nm, did a bit of further fine-tuning to the memory controller... presto! we have winchester. compare a newcastle 3500+ to a winchester 3500+, and they are almost exactly the same. in fact, winchester is a smidge faster, probably due to the memory controller tweaks.

you can't possibly call me biased there. i'm just saying that process size has NOTHING to do with performance at a clock speed, architecture does, and that's where intel is getting the flack, and amd isn't.

edit: intel added 11 stages to the pipeline. more than 50% longer. amd added 2, which is a 20% increase over K7.

Exactly, which was my point. That's what happened historically. Obviously the dieshrink itself didn't do anything...

man, you need to work on the way you phrase things. that is NOT how your previous statements came across.

 

[Scali]

scali.. man. haha, i dunno what to say. i said that simply scaling down the process size will not yeild any performance benefits.

Indirectly it will, as I described in my previous post.

you cannot argue that. the reason that intel normally gets more performance out of a smaller process is because they normally double the cache and try to make the core more efficient. this is a change to the core itself, if the northwood was scaled back to .18 microns like the willamette was, but didn't chage the basic core, it would behave exactly the same. only the electrical/thermal characteristics are changed.

I'm talking WAY back here. Like Pentium/PII era. Obviously the P4 changed dramatically with every die-shrink. As I also described in my previous post.

you can't possibly call me biased there. i'm just saying that process size has NOTHING to do with performance at a clock speed, architecture does, and that's where intel is getting the flack, and amd isn't.

You're very much biased, you only look at P4 architectures, because they suit the point you're trying to make. I never mentioned that I am talking about P4 specifically. In fact, the P4 is exactly the exception to the rule that I was talking about. And the Athlon64 is a similar exception.

edit: intel added 11 stages to the pipeline. more than 50% longer. amd added 2, which is a 20% increase over K7.

Excuse me? Where do you get those figures from?
I'd have to look up the actual tech docs... but I seem to recall that the Northwood was 28 stages, and the Prescott is 31 (you probably talk about the move from 20 to 31? 20 stages was the pipeline excluding the decoding stages, because of trace cache).
If it was really 50% larger, obviously the impact on latency and throughput would be huge, while the Prescott and Northwood still perform in a very similar way. So your figures can't possibly be right.

The K7 was 10 stages, and the K8 was 12?

 

[Scali]

man, you need to work on the way you phrase things. that is NOT how your previous statements came across.

How about you need to learn how to read clearly without putting your own bias upfront?
You're arguing about trivialities that we both understand. That is not exactly a nice way of discussing.

 

[Jason711]

none for sale eh?

 

[(cf)Eclipse]

nah, it's just the way you're saying things, and the way i interpret it. i actually find it really amusing that you keep saying that i'm biased, cause i'm trying really hard to keep this straight-forward

i'll give some examples of what i mean.

Other than that AMD seems to have the same problem as Intel when going from Northwood to Prescott... The CPUs run hotter, yet they don't really offer more performance

not true. i just said that AMD's 90nm processors run cooler (67w vs 89w) and are a weeeeee smidge faster than the 130nm ones.

scali, the way you phrased that, it makes it sound like just by simply moving to a smaller process, performance should jump up

That's what historically happened yes, and when it didn't happen for Intel for the first time in history, they got a lot of flack. So now it's only fair to give AMD the same amount of flack, since they 'failed' in exactly the same way. Unless you're biased ofcourse.

i touched on that too. simply moving to a different process doesn't effect performance, just the heat output. i'm not gonna go into what intel did here that caused them to get a lot of flack. though it appears that you touched on that while i was writing up my previous post. long story made short, i think we're arguing about the first quote in this post. i was trying to explain that a simple process change won't effect performance, though it seems i assumed too much, and you didn't state yourself clearly before, thus causing a mess


so, you still saying that AMD has failed with the 90nm transition, and that the winchester is hotter and slower than the newcastle?


edit: jason.. not yet time will tell though

 

[Jason711]

who brought the intel bullshit in a thread about venice core info? GO HOME!

 

[(cf)Eclipse]

*shrug*
i was just trying to figure out why he said what he did about amd's 90nm chips, and it scaled from there
you can always request a delete, though i think it's a useful debate.. though a bit trivial in the middle.

 

[Jason711]

debates are awsome... in a thread intended for them. however, this thread is already so damn big, now ppl just have to wade through more crap to find info about venice.

 

[(cf)Eclipse]

well frallan is summarizing most of the stuff in the first post, so it shouldn't really matter

 

[Jasonx82]

Any Venice Sightings yet?

 

[Jason711]

not that i know of..

 

[MaMMa]

boooooooooo

 

[cell_491]

yes booooooooooooooooooooo....i was looking forward to ordering one today...I got my DFI ultra-d and my fortron bluestorm 500watt today and i was looking forward to filling that empty cpu socket.

 

[n64man120]

how are they going to be price wise to comprable winnys?

 

[(cf)Eclipse]

how are they going to be price wise to comprable winnys?

hahaha, oh man
those of you in the know, feel bad for me now. this is #12

they should be the same, but with newcastle to winchester, we saw vendors inflating prices due to demand. the same thing will happen here, so expect 5-10% more.

 

[Scali]

nah, it's just the way you're saying things, and the way i interpret it. i actually find it really amusing that you keep saying that i'm biased, cause i'm trying really hard to keep this straight-forward

You're not doing a very good job at it.

not true. i just said that AMD's 90nm processors run cooler (67w vs 89w) and are a weeeeee smidge faster than the 130nm ones.

I wasn't comparing AMD's 130->90 nm transition to Intel's... as I said before, you can't compare them, because Intel also went from 32 bit to 64 bit during the die-shrink, while AMD went from 32 to 64 on 130 nm, and later shrunk to 90 nm.
I meant that AMD's new 90 nm core was hotter than the old 90 nm core (which should be obvious, because that's the topic at hand in this thread), even though performance was barely improved. So like with Intel the efficiency of the core has decreased.

so, you still saying that AMD has failed with the 90nm transition, and that the winchester is hotter and slower than the newcastle?

That is something we'll never know, because AMD never built any high-end models on their 90 nm process... Now they have a new core that finally has the potential to beat the high-end 130 nm models... but it's not as cool as the first 90 nm core.
With Intel we saw the opposite... the first 90 nm turned out to be very hot, and the later models, even with 2 mb cache added, run cooler.
But I guess in the end the result is pretty much the same. For both companies, 90 nm hasn't exactly made a lot of progress so far, performance-wise.

 

[(cf)Eclipse]

so you go from a die shrink to a 90nm->90nm conversion?

i'm done with this. if you really want to continue it, pm me. just leave the comments about being biased out of it.

 

[Scali]

so you go from a die shrink to a 90nm->90nm conversion?

I'm not 'going' from anything. This thread is about the new 90 nm core, which I (and many others in this thread) was comparing to the old 90 nm core. It's not my fault that you wrongly assumed something that fits your agenda better, even though it wasn't the topic of this thread. I even said 'the CPUs run hotter'... well if that's not a hint that I was talking about 90nm->90nm rather than 130nm->90nm, then I don't know what is.
I resent that you try to discredit me in this way. If you want to play low, do it against someone else. I like a mature, friendly discussion. Not this low underhanded stuff.

 

[crypt1c.0]

I am sorry, I hate to continue this, but that intel-baby/!!!!!! is driving me nuts. Dude... your getting a Dell!

You should read your tech docs before posting my friend, infact Intel did go from a 20 stage pipeline to 31 when moving from Northwood to Prescott. Intel has been doing poorly these past two years and they know it, hence the cancellation of the Pentium 4 netburst architecture.
Have you ever actually looked at benchmarks? Its amazing that a 2.2 GHz AMD64 can surpass an Intel EE in gaming benchmarks, especially when the Intel EE is what....1.2 GHz faster? Hmmmmm, curious isnt it. Oh yeah, did I also mention that Intel suffers from poor monoplistic business practices because they know there processors have sucked lately.

And in case you are wondering, I am not an AMD !!!!!!. It was quite the oppoisite, until the past 18 months I always bought Intel.
_________________________________________________________________________

Eclipse: I have all the parts I need to build my new rig minus the proc (waiting for venice) Thanks for all your advice.
Here are the specs:
AMD 3500+ Venice Core (ASAP)
DFI LanParty NF4 Ultra
OCZ 520 Modstream
1GB 2x512 Crucial Ballistix
2x 250GB 16MB Cache Maxtor Hard-drives
Plextor 16X DVD Burner
ATI x800XL 256MB
SoundBlaster Audigy 2zs Gamer
Logitech 5300e

 

[cell_491]

i wouldnt say intel is doing poorly...they may not have the fastest cpus but intel still holds MUCH more market share that amd, in other words they sell alot more pentium 4's than amd sells athlons

 

[crypt1c.0]

2 words for intels market domanice... Blue men!!!! The average american consumer is stupid. They buy what ever product has the best advertising.

 

[Scali]

I am sorry, I hate to continue this, but that intel-baby/!!!!!! is driving me nuts. Dude... your getting a Dell!

Oh please, I am far from a !!!!!!. If you know I'm getting a Dell, you should also know I have two Athlons.

You should read your tech docs before posting my friend, infact Intel did go from a 20 stage pipeline to 31 when moving from Northwood to Prescott. Intel has been doing poorly these past two years and they know it, hence the cancellation of the Pentium 4 netburst architecture.

Links please?
I already said that I thought your figures were wrong, but I haven't been able to find the proper docs yet. As I said, 20 stages is without the tracecache part, with tracecache part it will be 28 or something like that... It's a bit hard to compare things when you're not absolutely sure that you're comparing the same things. The beauty of tracecache is that part of the pipeline is not being used during execution, and instruction decoding is decoupled from execution altogether... So we should be comparing the effective pipeline length of both... which I sadly can't find any good docs on yet.
However, the latency and throughput figures of both cores would indicate that the effective pipeline has changed very little (I did find that one, right here: ftp://download.intel.com/design/Pentium4/manuals/24896611.pdf)

Have you ever actually looked at benchmarks? Its amazing that a 2.2 GHz AMD64 can surpass an Intel EE in gaming benchmarks, especially when the Intel EE is what....1.2 GHz faster? Hmmmmm, curious isnt it. Oh yeah, did I also mention that Intel suffers from poor monoplistic business practices because they know there processors have sucked lately.

Who cares about clockspeed? If anything, AMD-lovers should know that clockspeed means nothing, MHz myth and all. It's about value for money... Intel CPUs may run at higher clockspeeds, but you also pay less per MHz, so who cares? Just compare equally priced systems.
The real problem is that Intel suffers from very high memory latency, mostly because the controller is not on-die.
It's nice that AMD processors are faster at games, but I'm not much of a gamer so I don't really care about that. There are plenty of other benchmarks where P4s do quite well, so I'm happy with them.

You also seem to get quite upset for someone who's supposed to be neutral.

 

[cell_491]

2 words for intels market domanice... Blue men!!!! The average american consumer is stupid. They buy what ever product has the best advertising.

EXACTLY!! when was the last time you saw an AMD commercial...NEVER. Because of this intel will OWN the mainstream computer market for many years to come. I seriously wish AMD will advertise their athlons so next time I build a friend a gaming pc I dont have to explain to them what an AMD athlon is...lol

 

[Scali]

I seriously wish AMD will advertise their athlons so next time I build a friend a gaming pc I dont have to explain to them what an AMD athlon is...lol

Oh yea, their marketing department is such a bunch of amateurs
They had this commercial over here that claimed that the NX bit in their Athlon64 would protect your computer against viruses and such.
The ad was reported got pulled off the air because of gross misinformation

Anyway, AMD has a big problem... it's not a very healthy company... they have made losses for years, and they are barely breaking even now, I believe. So there just isn't a lot of money to invest in advertisement.

 

[(cf)Eclipse]

you have a good point there about the investment. though i've never seen an amd commercial.. ever.

 

[Jewball]

It is the 4th, where the hell is the Venice?!?!?!?!

 

[robberbaron]

you have a good point there about the investment. though i've never seen an amd commercial.. ever.

The only thing I've seen, and in pictures, is the Turion sky writing.

 

[(cf)Eclipse]

yeah, same here. i bet it was cool in person though.

 

[Hito Bahadur]

Links please?
I already said that I thought your figures were wrong, but I haven't been able to find the proper docs yet. As I said, 20 stages is without the tracecache part, with tracecache part it will be 28 or something like that...

Took 5 seconds of looking on Google:
http://www.lostcircuits.com/cpu/prescott/4.shtml

Qoute for the lazy: "Depending on the counting scheme applied, different numbers are floating around but on a 1:1 comparison basis, if Northwood pipeline stages are counted as 20, then the equivalent number of Prescott pipeline stages is 31. This increase in pipeline stages means that the number of clock cycles for data and instructions to reach the core has increased from 20 clock cycles to 31 cycles."

BTW: why put money to advertising dollars when they are busy ramping production. Sounds like a waste of money to me. And yes I am an AMD stock holder and have been for years.

 

[crypt1c.0]

Thanks Hito!

 

[Scali]

Took 5 seconds of looking on Google:
http://www.lostcircuits.com/cpu/prescott/4.shtml

Yes, I saw that link, but I can't consider that source a very reliable one... It doesn't say WHAT exactly they're comparing, and certainly not where they got their info from, so it cannot be verified. I found some info from Intel too... (http://www.intel.com/design/pentium4/prodbref/)

Hyper-Pipelined Technology
The hyper-pipelined technology of the Intel NetBurst microarchitecture increases the pipeline depth delivering increased performance, frequency, and scalability of the processor. One of the key pipelines, the branch prediction/recovery pipeline, is implemented in 31 stages on the 90 nm Pentium 4 processor, compared to 20 stages on the 0.13 micron Pentium 4 processor.

Apparently this is 'one of the key pipelines', and has to do with branch prediction/recovery.
I interpret that as the CPU looking further ahead to predict branches, in which case it would be an advantage, not a disadvantage. But what other 'key pipelines' are there then, and how long are they?
Oh well, I guess the P4 pipeline is just too complex to discuss as a single pipeline of n stages.
As I said before, it doesn't jive with the figures for latency and throughput from the Intel manuals.
Either the effective pipeline during tracecached code is not longer, or the extra length does not affect performance.
Whichever option it is, it's not exactly an interesting point to raise in this discussion. It's just a figure on paper.

 

[Hito Bahadur]

Yes, I saw that link, but I can't consider that source a very reliable one...

I'll try to find a quote from Tom's Hardware so you can be satisfied.

edit: To add promised quote http://www.tomshardware.com/cpu/20040201/

 

[Hito Bahadur]

Here's one comparing a Prescott 3.2 and a P4 EE 3.4:

http://www.hothardware.com/viewarticle.cfm?page=2&articleid=262&cid=1

Qoute for the lazy: "Deeper 31 Stage Pipeline:
Prescott's new deeper pipelined core has perhaps the most significant impact on the core's performance and future scalability. Versus a Northwood core, the extra 11 stages in Prescott's pipeline, will afford the processor much more headroom for clock speeds in the future. In fact, Intel has a 4GHz P4 on their roadmap this year, with 3.4 and 3.6GHz flavors right around the corner in Q2."

 

[Scali]

Here's one comparing a Prescott 3.2 and a P4 EE 3.4:

That still does not answer where they got their figures from, and what these figures describe exactly. Just look at my previous post... What key pipelines are there?
And listen to common logic: why are latency and thoughput barely affected? How is that possible if the pipeline got 50% longer?
Latency will always go up if you cut up your pipeline into more stages in order to scale to a higher clockspeed... that's the whole point, you have to reduce the maximum propagation time per stage, else you can't get to higher clockspeeds.
So there must be something else going on here.