I saw cageymaru posted this in the Ryzen leaked benchmarks thread, but thought it warranted its own thread:
https://hardforum.com/threads/leaked-amd-ryzen-benchmarks.1920876/page-21#post-1042831422
This is the article in which I saw this:
https://www.overclock3d.net/news/cp...a_exascale_mega_apu_in_a_new_academic_paper/1
Here's the actual paper:
http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf
This looks like a future APU aimed at HPC (or possibly gaming applications) that is very modular in nature using an interposer to glue different pieces together. I'm guessing this would use some future iteration of the Zen architecture for the CPU "chiplets" (kind of a funny term) and some version of Navi or later for the GPU chiplets. This seems like it would enable them to pack a lot of power in a single package.
There were a few things that stood out to me just looking at this. The advantage of this approach is that they don't have to deal with terrible yields of a huge chip. However, there are a lot of separate dies stacked together so manufacturing and testing the entire assembly would not be trivial/inexpensive. The memory stacked on the GPU "chiplets" will probably provide quite a large amount of memory bandwidth at the expense of being, well, more expensive. It seems like a good way to get a lot of power into a small package, but isn't the simplest design.
https://hardforum.com/threads/leaked-amd-ryzen-benchmarks.1920876/page-21#post-1042831422
This is the article in which I saw this:
https://www.overclock3d.net/news/cp...a_exascale_mega_apu_in_a_new_academic_paper/1
Here's the actual paper:
http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf
This looks like a future APU aimed at HPC (or possibly gaming applications) that is very modular in nature using an interposer to glue different pieces together. I'm guessing this would use some future iteration of the Zen architecture for the CPU "chiplets" (kind of a funny term) and some version of Navi or later for the GPU chiplets. This seems like it would enable them to pack a lot of power in a single package.
There were a few things that stood out to me just looking at this. The advantage of this approach is that they don't have to deal with terrible yields of a huge chip. However, there are a lot of separate dies stacked together so manufacturing and testing the entire assembly would not be trivial/inexpensive. The memory stacked on the GPU "chiplets" will probably provide quite a large amount of memory bandwidth at the expense of being, well, more expensive. It seems like a good way to get a lot of power into a small package, but isn't the simplest design.