Mother of All APUs

[Schmave]

I saw cageymaru posted this in the Ryzen leaked benchmarks thread, but thought it warranted its own thread:
https://hardforum.com/threads/leaked-amd-ryzen-benchmarks.1920876/page-21#post-1042831422

This is the article in which I saw this:
https://www.overclock3d.net/news/cp...a_exascale_mega_apu_in_a_new_academic_paper/1

Here's the actual paper:
http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf

This looks like a future APU aimed at HPC (or possibly gaming applications) that is very modular in nature using an interposer to glue different pieces together. I'm guessing this would use some future iteration of the Zen architecture for the CPU "chiplets" (kind of a funny term) and some version of Navi or later for the GPU chiplets. This seems like it would enable them to pack a lot of power in a single package.

There were a few things that stood out to me just looking at this. The advantage of this approach is that they don't have to deal with terrible yields of a huge chip. However, there are a lot of separate dies stacked together so manufacturing and testing the entire assembly would not be trivial/inexpensive. The memory stacked on the GPU "chiplets" will probably provide quite a large amount of memory bandwidth at the expense of being, well, more expensive. It seems like a good way to get a lot of power into a small package, but isn't the simplest design.

 

[CSI_PC]

It is definitely a concept for HPC as exascale is the next major milestone all the major tech companies are aiming for.
Far from easy to do and so far just concepts from all of them, especially within a certain Megawatts power demand criteria.
Energy efficiency with performance is going to be critical.

Cheers

 

[Schmave]

I finished reading the whole paper, and there are a few interesting things I noticed:

• There would be "active" and "passive" interposers on the device. The active interposers would actually have logic on them (such as memory controllers or other SOC related things) while the "chiplets" would be kept simpler than a current generation CPU or GPU as far as not having an IMC or some of the traditional "uncore" functions of a CPU.
• It may be desirable to tailor compute resources and memory arrangements to a particular application. There are a lot of trade-offs between performance, power consumption, memory size, etc. and certain workloads stress the system differently.
• "Threshold" voltage computing, i.e., running the voltage supply low enough to potentially cause errors would be a way to save power. The logic would have to be fault tolerant to do so.
• The "chiplet" approach allows one to use a manufacturing process that is optimal for that chiplet's function. GPU chiplets could be built on a different process than CPU chiplets, for example. Also the interposers can be manufactured on a more mature (cheaper) process.

So far it definitely sounds like just a research paper as they are investigating the feasibility of this for the 2022-2023 time frame. I don't think they have any products in the works, but I also wouldn't be surprised if there were some prototype designs in the works to test out different aspects of what they want to do.

 

[Marstg]

Didn't AMD say (or it was leaked somewhere) that the next desktop APU generation, the Raven Ridge will have HBM? That already will mark quite the jump in available graphics power. And from what I understand it will also pack 1024 CU, just like a 7850 enough to play at 1080p with maxed eye candy.

 

[Pieter3dnow]

Didn't AMD say (or it was leaked somewhere) that the next desktop APU generation, the Raven Ridge will have HBM? That already will mark quite the jump in available graphics power. And from what I understand it will also pack 1024 CU, just like a 7850 enough to play at 1080p with maxed eye candy.

HBM at this point in time makes those chips really expensive from a consumer point of view, but for server related matters it might be a niche segment that would use those.