Gateless Majority Logic

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
What it might look like if we chain 8 bits together for a full result...
Replacing two earlier drawings in this same post that had errors.

Fix20200918.png


Trying here to make better sense of several earlier messes.
Changed "Inhibit" to "Kill" cause "I" looked too much like "1".
Changed "CarryIn" to "EQ" cause it made better sense of the new comparator functions.
"C" never made sense for Borrow, especially since I don't get there by add with inversions.
Selection of conditional logic now hijacks Carry rather than Borrow, cause it drew easier.
Four bits might fit a module of 32 pins with power and /OE, if I were to build it...
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
The ALU above merits a barrel shifter.

Barrel.png


Since switches can all be thrown while the ALU churns, the only delay is propagation through two transmission gates. 250pS each...

Note that only 6 devices are needed. Not requiring the braindead obvious 8 multiplexers, each sweeping through 8 steps of rotation.
Also consider the parasitic spaghetti factor. Only four dead-ends splay out per bit, instead of the expected seven. Expand to 16bits,
the low row of plexers would then become 4way as well. 6 dead-end sphaghetti vs 15 the dumb way.

The best way might be seriously wasteful of devices. Full spread from results to intermediate sphagettiland with no shared strand.
Then a full scrunch to rotated results. Why? Because unused strands cut from both ends cease to present unterminated stubs.
You might be surprised how much problem an unexpected inch long echo can cause...
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
The offical name for these sort of switches would be "Transmission Gate". Below are
several common ways you might see them drawn in multiplexer spec sheets. Doesn't
seem to be much of an agreed standard across brands.

I was drawing them as-if relays. Overuse of that symbol ate too much space in my
drawings. Lately I'm drawing an abstract trapezoid to stand for a multiplex of several.
Somtimes I still prefer to draw finer details to explain some point or other.

Body diode given in the symbol for a stand-alone MOSFET would cause directional
leakage issues in a transmission gate. Fortunately, diodes in this situation connect
only to rails, not immediately to each source. MOS4 symbols I needed were already
in LTSpice. Just had to discover them.

TransmissionGates2.png


All gates are driven by internal pre-amps. Some amps offer protection features.
I didn't bother to draw all those amps, except the one case with a charge pump.
Just know they are there, and differ, and read your spec sheet before choosing.

Main gotchas to watch for:
74CBT needs VCC to be 2V higher than any signal you might want to pass.
74CB3Q has a charge pump, but power limited to 10 or 20 MegaSwitches/Sec.
74CBTLV can pass signals rail to rail, but PMOS isn't quite as fast as NMOS.
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Always troubleshooting someone else's board, never designing my own...

I need some layout software with minimal learning curve that can handle 2 layers and SSOP16.
The place I work for uses Altium. But its overkill, and the licence fee is rather extreme. Plus they
don't want me hanging around off the clock to use a company PC with an existing licence.

So I will probably try: What is free tier Altium called, Circuit Maker? I gather you are forced to
openly publish your projects. And thats probably to prevent commercial misuse. Dunno what
other limitations. If its way different than regular Altium, the guys at work may not be able to
help me. Ultimately I need Gerber compatible files to have a board made...

The alternative is a crapload of 50cent DIP adapters and Vero Board. Which will get me there,
but isn't reproducible if I want to expand. And parasitic sphagetti might slow things more than
prove anything fast.
 
Last edited:

paradoxical

Weaksauce
Joined
May 5, 2013
Messages
103
Always troubleshooting someone else's board, never designing my own...

I need some layout software with minimal learning curve that can handle 2 layers and SSOP16.
The place I work for uses Altium. But its overkill, and the licence fee is rather extreme. Plus they
don't want me hanging around off the clock to use a company PC with an existing licence.

So I will probably try: What is free tier Altium called, Circuit Maker? I gather you are forced to
openly publish your projects. And thats probably to prevent commercial misuse. Dunno what
other limitations. If its way different than regular Altium, the guys at work may not be able to
help me. Ultimately I need Gerber compatible files to have a board made...

The alternative is a crapload of 50cent DIP adapters and Vero Board. Which will get me there,
but isn't reproducible if I want to expand. And parasitic sphagetti might slow things more than
prove anything fast.

KiCad?
 

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
https://www.sciencemag.org/news/2020/09/short-weird-life-and-potential-afterlife-quantum-radar

"real entangled light pulses that experimenters can generate with a special crystal that converts a single higher frequency pulse to two entangled pulses at lower frequencies."
"Physicists can generate pairs of entangled microwave pulses from single ones using, instead of a crystal, a gizmo called a Josephson parametric converter."

Science news oversimplified to the point of nonsense. But sounds like Parametrons might have found a new use.

Recall the optical thingie of post #6. Keep in mind that an optical parametron excited by a single photon with no other logic input would generate a random binary phase shift.
Output at half frequency probably has to emit two photons for powers in and out to be equal. Returning strings of random key'd pulses may look like noise except when tested
for time and phase correlation to a copy kept locally in a delay line. It bugs me that radar would already have to guess the distance better than 1/4 wave before you could even
test wether there was a correlation. Or maybe thats why they are saying its 4 times better than regular radar? Not enough info here to be sure. I'm betting that light is not used,
but some really long microwave instead.
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Another iron I got in the fire but can't exactly call gateless, is pre-computed lookup tables in parallel MRAM or NVSRAM.
As FPGAs interconnects a bunch little bit vs bit lookup tables. I'm simply interconnecting a few larger byte vs byte tables.
64 such tables will fit in the current largest 32 Megabit MRAM (21 bits in, 16 bits out), or 32 functions with result & flags.

Why bother? Same 35nS to lookup the third byte after the fixed point of a COSine(AB) as it takes to lookup AND(A,B).
If I homebrew an 8 bit minicomputer that only runs a few MHz, arbitrary cheatsheet logic will somehow have to make
it impressive. So here's a proposed grand table of tables for the MRAM or NVSRAM that will serve as ALU. These are
just ALU functions, not instructions. IE: no jump to be found here. There will be another table to issue such microcode.

TableOfTables.png

I prefer to post as plain text, but forum won't tab and destroys spaced columns.
Not sure how forum "Insert Table" feature works yet, sounds promising maybe...

So, a pair of bytes found in the ALU table output to a pair of 74LVC373 latches.
Those latches then output to some, all, or none of three 32Kx8 register banks.
Couldn't find modern register banks smaller, cheaper, or less overkill than 32Kx8.
Register banks (together with microcode) form an address for the next ALU lookup.
Round robin in three steps, so input bits can be held valid while reading outputs.

First register bank serves the A argument.
Second bank serves the B argument.
Third bank (written bytewide, but read through an 8:1 MUX) serves the flag.
Completely ambidextrous, provided data was mirrored to all relevant banks.
Totally faking triple port memory on the cheap by throwing around extra copies.

Any bit stored to the 3rd bank can be indexed as active flag at a later time.
Test a non-flag bit from any result byte as-if it held flags? Fine, no problem.
Retrieve extra data hidden in unclaimed flag bits? Fine, no problem.

The first 256 bytes of register banks A&B should contain constants 00-FF. Perhaps a
routine at boot fills those volatile constants? Or spend the extra $5 and use an MRAM.
Either way won't need exceptions for indirect addressing. Just let everything be indirect.
Constants now imitate the missing direct mode.

Increment by +1 and +2 tables could serve as the program counter and skip next.
But I prefer the program count to be read in parallel time from a separate device.

Enough for now. We'll talk single argument tables when I got them in presentable order.
Good stuff: Binary Coded Decimal, Greycode, Cellular Automata, 16 Segment LED Font.
Maximum abuse of arbitrary cheat sheet logic...
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Strangely, this seems not to be a new idea at all.
IBM 1620 CADET "Can't Add Doesn't Even Try"
IBM_1620_Model_1.jpg

Abused both addition and multiplication tables
stored in non-volatile magnetic core memory.

Spintronic MRAM might then be Spin CADET?
Glorious...
 

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Some explanations will be required.

Subfunctions will use the B input byte to choose a subfunction.
Operate only on the A input byte, and maybe the state of carry.
I'll replace text with a picture later to make the columns line up.
Gotta get to work now, so can't worry too much how it looks.

The chosen flag going into each ALU lookup may also be cleared
or inverted by two bits of each instruction. In this way the flag may
carry as normal, or select uncarried functions from either column.

We also have the option to discard either byte or flag result when
the other is irrelevant or distracting. This is used to combine similar
functions with different targets when one posssible target is carry.

Since subfunctions operate within the limits of one byte, N and M
shall represent bit positions within the argument byte and result.
C represents a chosen input flag. Carry, Zero, and six uncommitted
flag bits output together as a byte. Separated only when referenced
by later instructions.

Might let the uncommited bits hold inverse flags and 01 constants,
would trim two bits off my instruction width. Still mulling whats best.

Code:
# 256 Single Input Byte FUNctions
# ignoring Carry Input still allows for an optional Carry Output
------------------------
64      AND (N,M) to C,M # Only 56 instances matter
64      IOR (N,M) to C,M # Only 56 instances matter
64      XOR (N,M) to C,M # Only 56 instances matter
64      SWP (N,M)        # Only 28 instances matter
Code:
# 256 + 256 Single Input Byte Functions
# FN0 + FN1 with Carry Input, or as modified by the instruction
-------------------------- Functions requiring Carry input
64 + 64 AND (N,C) to C,M # Only 56 + 56 instances matter
64 + 64 IOR (N,C) to C,M # Only 56 + 56 instances matter
64 + 64 XOR (N,C) to C,M # Only 56 + 56 instances matter
        CPY   N   to C,M # Alias of AND/IOR/XOR(N,C) coercing C input
        CPY   C   to  N  # Alias of SWP (N,C) inhibiting the C target
8 +  8 SWP (N,C)
8 +  8 ROT   N   to  C  # Rotate through Carry until N arrives at C
8 +  0 SLL   N   to  C  # Shift Left  to Carry, fill void w 0's
0 +  8 SRL   N   to  C  # Shift Right to Carry, fill void w 0's
8 +  0 SRA   N   to  C  # Shift Right to Carry, fill void w Sign
0 +  8 CIR   N   to  0  # Circulate sans Carry...
2 +  2 R30              # Wolfram's Rule 30 with bookends CxxxxxxxxN
# useful for pseudorandom number generation
# https://mathworld.wolfram.com/Rule30.html
1 +  1 CNT  All     0's # Count All 0's may include Carry in = 0
1 +  1 CNT  All     1's # Count All 1's may include Carry in = 1
Code:
---Below this line, C input acts not as a flag but further selects subfunction---
0 +  8 CVT  ASC  to TRM # 8x8 Terminal Font (likely 5x7 plus a decender)
0 +  8 CVT  ASC  to CON # 8x8 Console  Font (likely 5x7 plus a decender)
0 +  1 CVT  ASC  to NBL # Ascii Hexadecimal to Absolute Low  Nibble
0 +  1 CVT  ASC  to NBH # Ascii Hexadecimal to Absolute High Nibble
0 +  1 CVT  NBL  to ASC # Absolute Low  Nibble to Ascii Hexadecimal
0 +  1 CVT  NBH  to ASC # Absolute High Nibble to Ascii Hexadecimal
0 +  1 CVT  ASC  to 8SG # Ascii to  7 Segment LED Low  Byte with Dot
0 +  1 CVT  ASC  to 14L # Ascii to 14 Segment LED Low  Byte
0 +  1 CVT  ASC  to 14H # Ascii to 14 Segment LED High Byte with Dot
0 +  1 CVT  ASC  to 16L # Ascii to 16 Segment LED Low  Byte
0 +  1 CVT  ASC  to 16H # Ascii to 16 Segment LED High Byte, ref 14H Dot
# https://www.partsnotincluded.com/segmented-led-display-ascii-library/
0 +  0 CVT  SGN  to ABS # alias of AND(A,7Fh)
0 +  0 CVT  ABS  to NEG # alias of RSB(0-A)
0 +  1 CVT  TWC  to ABS # Two's Complement to Absolute Value
0 +  1 CVT  ABS  to REV # 76543210<>01234567
0 +  1 CVT  GRY  to ABS # Greycode to Absolute
0 +  1 CVT  ABS  to GRY # Absolute to Greycode
0 +  1 CVT  BCD  to ABS # Binary Coded Decimal to Absolute
0 +  0 CVT  ABS  to BCL # alias of MOD(A/100d)
0 +  0 CVT  ABS  to BCH # alias of DVL(A/100d)
0 +  1 CNT Leading  0's # carry does not lead or trail
0 +  1 CNT Leading  1's # carry does not lead or trail
0 +  1 CNT Trailing 0's # carry does not lead or trail
0 +  1 CNT Trailing 1's # carry does not lead or trail

Numbers to the left are just counting subtables to be sure how many might fit.
Some are freebies, I list alias only to remind myself they aren't really missing.
I have a more complete list somewhere, but again the time right now is short.
Read this post again later, it will change.

Thinking to save the whole flag result byte to a third 32Kx8 for triple ported
simultaneous access. Worry individual bits when the flag is later referenced.

Did you know an NTSC color burst crystal sings 13 octaves above A437?
Divide by a full 16bits gives half wave time at the lowest note on the piano.
There's a table that corrects that to A440 and 11 other notes, just saying...
https://en.wikipedia.org/wiki/Colorburst
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Regarding the multiplexor based ALU of just a few posts ago.
Turns out iNTEL's 8086 leveraged many of the same tricks.
What follows is Ken Shirriff's drawing, not mine.
alu-schematic-w750_downscale.png

Manchester carry chain, MUX with changable inputs, etc.
Seems I can't come up with anything original. Go figure,
surprised as any by what was found under 8086's lid...

http://www.righto.com/2020/08/reverse-engineering-8086s.html
Compare to my drawings from posts #51 and #81.
 
Last edited:

XoR_

[H]ard|Gawd
Joined
Jan 18, 2016
Messages
1,107
OMG
I love the concept. Gonna read it all, few times at lest!

So far my neurons majority voted I should analyze first posts to get a good feel how it works... because surprise surprise I have no idea 🤯

EDIT://
Actually for few last years I wondered if one could create computers differently using analogue components and if that could be better base than transistors (read: controlled switches) and this looks like answer for my prayers. Kudos for you for bringing this enlightenment to us simple people 🤩
 

Nobu

Supreme [H]ardness
Joined
Jun 7, 2007
Messages
5,452
Fwiw, the
Code:
[code]
block is what you want. You can specify the language too, if you want, for coloration and to change how tab space is handled. ;)
 

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
OMG
I love the concept. Gonna read it all, few times at lest!

So far my neurons majority voted I should analyze first posts to get a good feel how it works... because surprise surprise I have no idea 🤯

EDIT://
Actually for few last years I wondered if one could create computers differently using analogue components and if that could be better base than transistors (read: controlled switches) and this looks like answer for my prayers. Kudos for you for bringing this enlightenment to us simple people 🤩
Half my old posts don't make sense even to me who wrote them.
Just move on to the others that do. There have been lots of errors,
not knowing in advance where any of it might lead.

NAND and NOR are universal logics that combine to make any other.
Long known and taught, the proofs are almost self-evident. But these
are not the only universal logics.

Inverters aren't normally universal, but can fake it by abusing power
as a logic input. The same trick also works to give XOR universality.

MINority logic easily makes NAND and NOR, thus proven universal.
4Way MUX makes NAND, NOR, MIN3 MAJ3 and several others.
2Way MUX can combine to make 4Way MUX, universal as well.

But there are important differences between asynchronus logics that
allow for immediate output change whenever the inputs may glitch,
vs synchronus logics that latch a new answer only when clocked.

The most extreme synchronus logics may not even have a fixed
direction of forward flow, but rely on a rolling blackout of any old
latched results to draw new logic results forward into its wake.
Quantum often operates in this category, as do parametrons.

Error: MIN3 can't be wired from a single MUX, not even a 4Way.
Takes at least a pair of MUX working together. Still not difficult...
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Fwiw, the
Code:
[code]
block is what you want. You can specify the language too, if you want, for coloration and to change how tab space is handled. ;)
Still drops leading spaces, but other column alignments look better.
 

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
So, quantum parametrons are not oldskool parametrons simply colder...
The quantum digit is a clockwise or counterclockwise flow of DC current.
Not exactly the binary phase shift keyed AC digit of the past. AC is used
to pump a DC bias around the loop. A new concept that at first, second,
or third conventional glance makes no sense whatsoever.

Lets begin by understanding a little about the two Josephson Junctions
that almost but not quite break the loop into two halves. DC supercurrent
can still flow around the loop without resistance. Up to some point where
junctions are tunneling all the supercurrent they can, and begin to resist.

They stop tunneling cooper pairs and begin tunneling unpaired electrons.
Resistance brings current down to where it can tunnel as pairs again.
Then lack of resistance allows current to again saturate the junctions.
And this process repeats. Oscillating resistance creates both an AC
and DC voltage drop across both junctions.

Now you begin to see why it takes two junctions, so each can undo
the voltage drop of the other and complete the loop with no voltage.
But there can be meaningful voltages between one side and the other.

Whats really weird is this process also works in reverse. If we put AC
excitation of appropriate frequency across the junctions, a DC bias will
automagically flow around the loop in response. Without resistance it
quickly builds to the critical limit in one of either possible directions with
no preference. Unless purposely upset by votes from an input circuit,
in which case it will flow with the same direction as the majority vote.

I still don't get how it clocks the DC current and its associated flux to
another loop. Its considered a destructive readout is all I got so far.

I'm also convinced junction size and critcal current must not be so
severely restricted as to supertunnel around a lone quanta of flux.
Needs to drive fanout, and you probably can't fanout from a single.
If transfers of flux can be adiabatic and free of loss, what further
power is saved by downsizing to the point you can't split a result?

There was a drawing to go with, but only made more confusion.
I'll attach later, after I figure a redraw for better sense.
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
635
Para1.png


IO is center tapped. So Excite may be coupled to IO, but not in an overt transformer way.
The IO side supports a loop of DC supercurrent (through ground and two Josephsons).
AC excitation mandates spontaneous DC bias appear, but doesn't care which direction.
Probably because no resistance, a fully saturated loop of DC all too easily happens.
How clocking excite can move that DC to other loops, I'm still working to understand.

Hmm, perhaps the lowest energy thing for an idle loop of electrons to do is circulate
to properly bias AC activity already at the junctions? If a slight excess of AC pumping
can excite a slight excess of DC self-bias, there should be a DC voltage drop tween
the IO midpoint and the other side of the loop, which also happens to be ground.
Does positive or negative DC Voltage here reveal the direction of loop current, or
does-not-care? Could Voltage simultaneously encode a separate bit from currrent?
 
Last edited:
Top