By definition, if you replace the fixed function shaders in the geometry engines with generarilzed non-compute shaders, they become programmable and thus of course they can be arbitrarily switched between behaving like Fiji's geometry engine and behaving like primitive shaders instead as needed.
Look, here is a slide from the Polaris slide deck:
By definition, are you trying to tell me something different than what the entire computer industry has been doing since the 50's? Polaris isn't do what Vega's primitive shaders are doing. Vega's traditional fixed function pipeline is doing the same as Polaris though. Hence the same problems. 4 tris per clock, if they changed the fixed function units to programmable ones, even with emulation that problem can easily be solved. Cause the problem is not a software limitation, its hardware limitation, so if that hardware is now changed, that limitation disappears (even when emulating the old fixed function pipeline), understand? It will no longer be stuck at 4 tris per clock, The fixed function units were done for one reason, to save die space, less transistors, and performance. This is why AMD didn't replace them, its clear as day in the white paper, it has both pipelines, fixed function and programmable and they are not the same units. There is no questioning what it has or doesn't have or its been changed.
Doesn't work that way.
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and here is were primitive discard is talked about in the Polaris whitepaper:
This makes it very clear that Polaris' Primitve Discard Accelerators are inside the geometry engines prior to the rasterizers, yes?
Not talking about rasterizer, its being done before tessellation. Polaris's discard is still not that efficient, still way behind its competitors with polygon throughput by close 50% comparing to equal cards. And they even talk about that in the white paper too cause its not doing the discard till after tessellation, Vega with primitive shaders fixes that problem, but while using its traditional fixed function pipeline still has the problem.
This shows primitive shaders being prior in the rendering pipeline to fixed function PDA culling. This is before the draw stream binning rasterizer on the Vega block diagram. What you are suggesting would mean that geometry would be being sent to the CUs for processing and then brought back through the chip to be put through the PDA fixed function culling and the four draw stream binning rasterizer. That doesn't make any sense, and no one would even try such a thing.
Yeah to do that they can't use the fixed function portion (tesselator) they have to emulate that in CU's as well. Vega has both fixed function units and can emulate those fixed function units in its CU's, it has to no way around it cause I stated before its in the white paper as such and if they do it any other way it will create problems for Dx certification and will cause a lot more work on AMD's part for older Dx games.
Incidentally, the Polaris slide deck conveniently proves that MSAA performance is a known geometry throughput issue for GCN, which is convenient.
well no its also bandwidth, a problem area of GCN since the r3x0 line.
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