Yes.So, not knowing the MB architecture very well (actually not well at all), and no block diagram, does each CPU control one of the dedicated I2C busses?
One per CPU. If you visually inspect the board you'll find them.Core32 said:On the 4P, is there one IR3521 per CPU or does one control multiple xPHASE3 chips which in turn provide core voltage for all CPUs?
That's I2C so clock always origins in the master and is only driven when the masterCore32 said:I will spend some time looking for a simple micro I'm comfortable with that can hang on their HS bus. I'll need to consider whether to use an on board clock or if it's OK to use the built in micro clock.
is transmitting (both lines are high when the bus is idling) -- unless AMD's tweaked the
protocol so clock is always on (unlikely).
Also, one doesn't really need to perform HS transmission (3.4 MHz); only one CPU rev
supported that (C3) and our CPUs of interest (D1) only support 400 kHz.
May even be able to use on-uC I2C...
I'm fine with it so far but if someone else feels we've crossed the line then we couldCore32 said:And should I/we start a seperate thread for this since I've managed to hijack this one badly?
probably ask a mod to extract this discussion into separate thread.