Supermicro H8QGi/6 and H8QGL Next Generation OC BIOS

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R-Type said:
If your chip has lower stock voltage it is going to top out below that for sure. I am very interested in seeing some real anecdotes though.
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My 6166HEs will be tested here soon as I get a little free time. musky feels they should be able to do a pretty good OC.
 
New ROM is available. A number of early adopters
reported HT-related issues with refclocks above 230.
This should be fixed now.

See OP for URL.
 
Some CPU / refclock / temp threshold* sets from various setups:

tjmagneto: 6176 SE / 231 / 50 deg
tear: 6174 / 225 / 60 deg
tear: 6180 SE / 225 / 50 deg (preliminary)

*) running above threshold is bound to crash the WU and/or system
 
Hopefully this is OK to post.
Using version 1, stable, not fully stretched out:

Core32: 6128 / 227 / (38 - 47) deg in a 2U server
 
Never thought we would get so excited about 10-20% overclocks again :)
 
AMD does something I like to call "fine-binning".

My 6174s:
Code: 
$ sudo tpc -l | grep 0.pstate.0
core 0 pstate 0 - En:1 VID:37 FID:6 DID:0 Freq:2200 VCore: 1.0875
core 0 pstate 0 - En:1 VID:37 FID:6 DID:0 Freq:2200 VCore: 1.0875
core 0 pstate 0 - En:1 VID:40 FID:6 DID:0 Freq:2200 VCore: 1.0500
core 0 pstate 0 - En:1 VID:40 FID:6 DID:0 Freq:2200 VCore: 1.0500
core 0 pstate 0 - En:1 VID:39 FID:6 DID:0 Freq:2200 VCore: 1.0625
core 0 pstate 0 - En:1 VID:39 FID:6 DID:0 Freq:2200 VCore: 1.0625
core 0 pstate 0 - En:1 VID:38 FID:6 DID:0 Freq:2200 VCore: 1.0750
core 0 pstate 0 - En:1 VID:38 FID:6 DID:0 Freq:2200 VCore: 1.0750
 
So it's now economical to get 6168's at half the price if 6174's and tweak to 6174 speeds.

Is it fairly simple process?

Anyonr know of ceap places in Canada for Boards?
 
I've got 68's but I lack a SM board, so I can't push that theory
 
rhavern said:
+10% of 2.3GHz across 48 cores is non-trivial :cool:
Click to expand...

ten percent OC

10 % of 2.3 Ghz is 230 Mhz

230 Mhz times 48 cores = 11,040 Mhz or 11 Ghz

fifteen percent OC

15 % of 2.3 Ghz is 345 Mhz

345 Mhz times 48 cores = 16,560 Mhz or 16.5 Ghz

twenty percent OC

20 % of 2.3 Ghz is 460 Mhz

460 Mhz times 48 cores = 22,080 Mhz or 22 Ghz
 
The other question, do the cheap 6128s look good for getting a 4P started on a budget, and what kinda OC will they take?
 
Taken a pair of 6128s to 2.57GHz back in the day.
NG2 (software-wise) should be good through 250 MHz base (2.5GHz on 6128s).

Core32's 4p is the closest to a test system except his cooling is stock which
may be a limiting factor... (the higher OC the lower operating temp threshold).

Anyone else with Gi/6 and 6128s?
 
Here are the vcore numbers for my 6128s:

H8QG6:~$ sudo tpc -l | grep 0.pstate.0
core 0 pstate 0 - En:1 VID:30 FID:4 DID:0.00 Freq:2000 VCore:1.1750
core 0 pstate 0 - En:1 VID:30 FID:4 DID:0.00 Freq:2000 VCore:1.1750
core 0 pstate 0 - En:1 VID:31 FID:4 DID:0.00 Freq:2000 VCore:1.1625
core 0 pstate 0 - En:1 VID:31 FID:4 DID:0.00 Freq:2000 VCore:1.1625
core 0 pstate 0 - En:1 VID:29 FID:4 DID:0.00 Freq:2000 VCore:1.1875
core 0 pstate 0 - En:1 VID:29 FID:4 DID:0.00 Freq:2000 VCore:1.1875
core 0 pstate 0 - En:1 VID:30 FID:4 DID:0.00 Freq:2000 VCore:1.1750
core 0 pstate 0 - En:1 VID:30 FID:4 DID:0.00 Freq:2000 VCore:1.1750

Now running at 230:
H8QG6:~$ dmesg | grep -o Detected.*
Detected 2300.188 MHz processor.

Temps while folding:
Temperature table:
Node 0 C0:41 C1:41 C2:41 C3:41
Node 1 C0:40 C1:40 C2:40 C3:40
Node 2 C0:34 C1:34 C2:34 C3:34
Node 3 C0:32 C1:32 C2:32 C3:32
Node 4 C0:37 C1:37 C2:37 C3:37
Node 5 C0:37 C1:37 C2:37 C3:37
Node 6 C0:34 C1:34 C2:34 C3:34
Node 7 C0:34 C1:34 C2:34 C3:34

Have not tried pushing above 230 so far. I'm thinking I will run a complete -bigadv after every adjustment to check the stability.
 
I have 4 X 6128 watercooled. At the moment they are folding at 38c, but unfortunately on the H8QGL, so it may be some time before I can post OC results. But if they can OC over 2.5, they must be one of the better $ per PPD out there.
 
enigma97 said:
R-Type which 61xx you are OC?
Click to expand...

They are extra spicy magny cours dodecas with no counterpart model in AMD's retail chips, they are differentiated by having fully unlocked control of the core multiplier, northbridge multiplier, and voltage for each. I have several points of data on the speed/voltage curve unfortunately most would be of little value to retail chips as I am running my voltage higher. I have had them as high as 3.3ghz/2.4ghz NB @ 1.3375v/1.1v folding stable, this was good for 300k+ ppd in 2p configuration (while drawing more power than a 4p ;).

I was recently thinking back to the volt mods we used to due to video cards using pencil lead or removing a resistor or two. Would something like the maybe be feasible for bumping voltage by a predictable amount?
 
R-Type said:
Ah very good. In that case let me tell you my dodeca's are rock stable at 3.0ghz with 1.275v, just maybe if you can keep your chips cool enough.... ;)
Click to expand...

Mmm, can't wait to tweak mine then :drool:
 
I've looked for a schematic of these G34 boards but have yet to find one.
I have a second barebones on order that I could work voltage with IF I can find the correct documentation.
I have enough soldering tools to do the mods, as long as it's not BGA mounted :eek:

Not sure if I posted this info before, but my TPF for a 6904 was cut from over 33min. stock to mid 27min. with the 230 OC using version 2 of this BIOS.
Excellent work! Thanks again.
 
The quickest way is reverse engineering AMD's SVI protocol (I2C-based),
then plugging another I2C master into the bus (uC of sorts) and driving the
VRMs manually.
 
Hi.:)

With this new OC bios, is the CPU voltage the only limitation for high refclock or not ?
 
tear said:
The quickest way is reverse engineering AMD's SVI protocol (I2C-based),
then plugging another I2C master into the bus (uC of sorts) and driving the
VRMs manually.
Click to expand...

The new master (ST, PIC, etc.) would need to intercept the present I2C steam and "adjust" to accordingly new levels, then transmit on as if the master.
Not sure I can reverse engineer the code itself since I have not seen it. But if I knew schematically where to capture the I2C stream and knew the device being sent the stream, it's likely I can interpret the captured I2C codes. Then it would be a matter of pipelining the I2C input to output and replacing the parameters that set the voltage.
Still, with no MB documentation, it's just a dream ;)
 
Not necessarily intercept.

I thought so too initially but later realized we don't really need to intercept
and adjust. We can let CPUs drive the VRMs at boot (the way they want)
and after CPUs have booted (P-state 0) we can just send custom SVI
command from another master.

The way I understand things, SVI commands are only sent on P-state
transition == as long as we guarantee no p-state changes occur (and
they do not occur post-boot if PowerNow is disabled)... so we should
be fine with second master, I _guess_.
 
Also, we don't need schematics as long as we locate
all CPU VRM controllers (and I did that a while back,
just need to dig the notes up).
 
Tear, can I help with a H8DG6-F. Also, have we tried doing this in an ESXi Ubuntu virtual machine?
 
tear said:
........ we can just send custom SVI command from another master.........
............. so we should be fine with second master, I _guess_.
Click to expand...

And if there are no other masters on that particular I2C bus. Not likely, I suppose, since in my experience, I2C is not used very often for a multi-master design.
Do you have the VRM (slave device) part numbers?
 
The only other master is the CPU. There are four dedicated busses.
I doubt transmission from uC (while CPU is idling) will screw the CPU up.

Anyway, it merely takes an attempt and I'm trying to be open minded here.

I've got info on the controllers but not here (I happen to be at work atm).

UPDATE: you're looking for IR3521 controller.
 
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tear said:
The only other master is the CPU. There are four dedicated busses.
UPDATE: you're looking for IR3521 controller.
Click to expand...

Thanks again for the info. I found the datasheet on those. Very AMD specific chip. :cool:
So, not knowing the MB architecture very well (actually not well at all), and no block diagram, does each CPU control one of the dedicated I2C busses?
On the 4P, is there one IR3521 per CPU or does one control multiple xPHASE3 chips which in turn provide core voltage for all CPUs?
With a quick look at the spec. I think that's possible but not sure if it's reasonable for this application.
I will spend some time looking for a simple micro I'm comfortable with that can hang on their HS bus. I'll need to consider whether to use an on board clock or if it's OK to use the built in micro clock.

I would like to persue this path more but might as well ask the hard question now :)

How much OC flexibility or speed advantage do you estimate can be gained by grabbing voltage control? I don't have enough direct CPU OC experience to begin on that one.

And should I/we start a seperate thread for this since I've managed to hijack this one badly? :D
 
Core32 said:
How much OC flexibility or speed advantage do you estimate can be gained by grabbing voltage control? I don't have enough direct CPU OC experience to begin on that one.
Click to expand...
slight voltage bumps are very helpful allow significant clock speed head room. R-Type has a couple posts in this thread with his experiences. He's been as high as 3.0ghz.
 
Also, consider that as TPF decreases, PPD increases non-linearly.
 
jebo_4jc said:
slight voltage bumps are very helpful allow significant clock speed head room. R-Type has a couple posts in this thread with his experiences. He's been as high as 3.0ghz.
Click to expand...
3.3ghz, and 2.4ghz northbridge.

3.0ghz is as high as I've been at anything close to your standard voltages.
 
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