How does the Intel E8500 Work?

[Duke3d87]

So, i found this diagram online...

It says 5.3 GB/sec reading/controller (there seems to be 4 of them).

Is it dual channel DDR2 400 - 6.4 GB/sec and only 5.3 GB/sec is reserved for reading?

x86 secrets talks about an XMB and an IMC. What are they?

is the XBM a memory controller? If it is, Intel's chipset is starting to look more and more like the hurricane. It would be intersting to see them modify it for FBDIMM.

 

[savantu]

All the info you need is here :

http://download.intel.com/design/chipsets/e8500/datashts/30674501.pdf
http://download.intel.com/design/chipsets/e8500/datashts/30674601.pdf

Enjoy !

*Large pdfs , better download them first.

 

[Duke3d87]

thank you. The first few pages answered my question. It is starting to look like the hurricane chipset. I like the idea of the 4 exernal chipsets and the NB just there to coordinate what goes on in the chipsets.