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How does the Intel E8500 Work?

D

Duke3d87

Limp Gawd
Joined
Jul 6, 2004
Messages
430
So, i found this diagram online...

huivso.jpg


It says 5.3 GB/sec reading/controller (there seems to be 4 of them).

Is it dual channel DDR2 400 - 6.4 GB/sec and only 5.3 GB/sec is reserved for reading?

x86 secrets talks about an XMB and an IMC. What are they?

is the XBM a memory controller? If it is, Intel's chipset is starting to look more and more like the hurricane. It would be intersting to see them modify it for FBDIMM.
 
thank you. The first few pages answered my question. It is starting to look like the hurricane chipset. I like the idea of the 4 exernal chipsets and the NB just there to coordinate what goes on in the chipsets.
 
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