At the RISC-V Summit, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The RISC-V SweRV Core is a 2-way superscalar design with a 32-bit, 9 stage pipeline core that allows for several instructions to be loaded at once and executed simultaneously. The 1.8GHz power efficient design uses 28mm CMOS process technology and will be featured in flash controllers and SSDs. These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. "As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today's wide-ranging data-centric applications," said Fink. "Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries."