Monolith2013
Limp Gawd
- Joined
- Jul 29, 2008
- Messages
- 130
http://jobview.monster.com/SR-PHYSICAL-DESIGN-ENGINEER-Job-Huntsville-AL-US-84981297.aspx
They have a listing for Physical Design Engineer in Huntsville, AL... Just thought some of you might be interested in this one.
SR. PHYSICAL DESIGN ENGINEER
SENIOR PHYSICAL DESIGN ENGINEER #1231593
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure,
- Static timing analysis, power and noise analysis and back-end verification across multiple projects.
MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 7+ years of experience in large VLSI physical design implementation and methodology for processes 65nm or smaller.
- Successful track record of delivering products to production is a must.
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route.
- Working knowledge of deep sub-micron routing issues as they relate to power and timing.
- Circuit level comprehension of time critical paths. Spice experience a plus.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Talus/Blast/Quartz), Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), MentorGraphics (Pinnacle/Olympus) .
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM
Apply Online
They have a listing for Physical Design Engineer in Huntsville, AL... Just thought some of you might be interested in this one.
SR. PHYSICAL DESIGN ENGINEER
SENIOR PHYSICAL DESIGN ENGINEER #1231593
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure,
- Static timing analysis, power and noise analysis and back-end verification across multiple projects.
MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 7+ years of experience in large VLSI physical design implementation and methodology for processes 65nm or smaller.
- Successful track record of delivering products to production is a must.
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route.
- Working knowledge of deep sub-micron routing issues as they relate to power and timing.
- Circuit level comprehension of time critical paths. Spice experience a plus.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Talus/Blast/Quartz), Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), MentorGraphics (Pinnacle/Olympus) .
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM
Apply Online