Tyan S8225 - Memory memory configuration help

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Sep 10, 2019
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Hi there, I have a tyan S8225 with 2x Opteron 8 cores each.
Can anybody please help me understand what is the memory limitation here?

I'm reading the manual and it's everything but clear to me:

https://www.tyan.com/Motherboards~S8225~S8225AGM4NRF~documents~EN

Relevant pages: 26-27-28

e.g. I really don't get the SR/DR reference on page 27.


Essentially I'm looking to have 64GB running as fast as possible, so could I have 8x Samsung M393B1K70BH1-CH9Q1 and have them running at full speed (1333MHz)?

What would I need instead to go for 64GB at 1600MHz?

Thanks!
 
Last edited:
Joined
Sep 10, 2019
Messages
24
i cant d/l that at work but its probably single rank/dual rank


ScreenShot081.png


ScreenShot082.png


ScreenShot083.png
 
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4x16 u/r sr would be the best. if im reading it right.

Ok cool, according to the second image SR/DR can run at the same frequency (1600MHz), but the very last image I uploaded states that Tyan recommends DR over SR.
I did my reading and some people mention that the advantages of SR are not that visible and somehow for certain operation DR does performs better. So there's no real performance advantage on SR over DR...?
 

pendragon1

Fully [H]
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Oct 7, 2000
Messages
23,474
i guess it depends on the situation. in reality you probably wouldnt notice the difference unless you looked for it through benchmarks.
 

Shikami

Gawd
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Messages
742
There is a performance difference to dual rank and lesser to single rank, but not in the manner that you will be thinking. It is about a few percentages in difference and can be worth it. I personally prefer it, and unfortunately can be hard to find since most of the crucial information such as command rate and ranking are hidden even on their web page technical summaries, or even within the documents of said DIMM. Although, most users will go by commands per T, bandwidth, clock, and GB/s the processor goes by page hits. To, note most processor controllers DO NOT support many of the over-clocking features that the RAM has been created for, such as 1T at so many per channel installed and clock, etc.

The integrated controller(s) are usually dual; and at times quad. The controllers act in difference (q.v. AMD's ganged and un-ganged) not much in unison and are mapped monolithic like. Think of the mapping of as like this:


Dual rank DIMM 0------------------------ rank 1 / rank 2

Dual rank DIMM 1------------------------ rank 1 / rank 2


So, in the above example DIMM 0 rank 1 can be refreshed, but rank 2 of DIMM 0 can have a page hit. Since it is dual controllers that can be 2 refreshes and 2 hits, but also it can be interleaved. Back in the day you had to fill all the banks just to get interleaved with a single controller, but the controllers now can interleave the mappings of the DIMM in full occupancy of the banks or in half; obviously not in single bank occupancy.



Single rank it would be like this:

Single rank DIMM 0------------------------ rank 1

Single rank DIMM 1------------------------ rank 1


In the above example DIMM 0 can be refreshed while DIMM 1 has a page hit and can be interleaved.



See what I mean now? The only issue is topology type, ranking support, and use of UDIMM , RDIMM, etc-meaning the limitations of the memory controllers as you install per channel and rank. As you install more you have start to have the need for logics on the DIMM's to cooperate with the memory controller or at times lower the clocks due to the limitation of board, EFI/RFI, crosstalk, etc. It is all dependent on architecture and support of the topology and memory controller.

Some people want memory, some want speed, some want hits. You decide by documentation and what the computer will most likely be processing for.


For example here are two reviews in which show the minor difference between SR (https://www.tomshardware.com/reviews/gskill-ripjaws-v-ddr4-2666-16gb-review) and DR (https://www.tomshardware.com/reviews/gskill-ripjaws-v-ddr4-2666-16gb-review).
 
Last edited:
Joined
Sep 10, 2019
Messages
24
There is a performance difference to dual rank and lesser to single rank, but not in the manner that you will be thinking. It is about a few percentages in difference and can be worth it. I personally prefer it, and unfortunately can be hard to find since most of the crucial information such at command rate and ranking are hidden even on their pages or in documents. Although, most users will go by commands per T, bandwidth, clock, and GB/s the processor goes by page hits. To, note most processor controllers DO NOT support many of the over-clocking features that the RAM has been created for, such as 1T at so many per channel installed and clock, etc.

The integrated controller(s) are usually dual; and at times quad. The controllers act in difference (q.v. AMD's ganged and un-ganged) not much in unison and are mapped monolithic like. Think of the mapping of as like this:


Dual rank DIMM 0------------------------ rank 1 / rank 2

Dual rank DIMM 1------------------------ rank 1 / rank 2


So, in the above example DIMM 0 rank 1 can be refreshed, but rank 2 of DIMM 0 can have a page hit. Since it is dual controllers that can be 2 refreshes and 2 hits, but also it can be interleaved. Back in the day you had to fill all the banks just to get interleaved with a single controller, but the controllers now can interleave the mappings of the DIMM in full occupancy of the banks or in half; obviously not in single bank occupancy.



I was single rank it would be like this:

Single rank DIMM 0------------------------ rank 1

Single rank DIMM 1------------------------ rank 1


In the above example DIMM 0 can be refreshed while DIMM 1 has a page hit and can be interleaved.



See what I mean now? The only issue is topology type, ranking support, and use of UDIMM , RDIMM, etc-meaning the limitations of the memory controllers as you install per channel and rank. As you install more you have start to have the need for logics on the DIMM's to cooperate with the memory controller or at times lower the clocks due to the limitation of board, EFI/RFI, crosstalk, etc. It is all dependent on architecture and support of the topology and memory controller.

Some people want memory, some want speed, some want hits. You decide by documentation and what the computer will most likely be processing for.


For example here are two reviews in which show the minor difference between SR (https://www.tomshardware.com/reviews/gskill-ripjaws-v-ddr4-2666-16gb-review) and DR (https://www.tomshardware.com/reviews/gskill-ripjaws-v-ddr4-2666-16gb-review).


Thank you this is very informative. It is difficult to find something that has a good balance between performance and especially cost.
Based on all the reading here and elsewhere I was thinking to go for the

Samsung M393B2G70BH0-CK0Q9

They are relatively cheap and readily available second hand which is what I'm looking for really. There's still something that puzzled me though... it seems like for 4x16GB I need to use the A1/B1 slots (as per diagram above), not sure it's me but those are the black slots which sound like old/slow. Am I not expected to use the blue slots instead? although they are marked as A0/B0...

S8225_2D.jpg

Thanks for all the help!
 

Shikami

Gawd
Joined
Apr 5, 2010
Messages
742
You mean CPU 0 2x16GB, and CPU 1 2x16GB....yes in second and fourth banks. It wont make anything less, unless according to the chart will make it less in performance. That is just the topology. Wow, looked up the DIMM and it was $40 beans o0! BUT, it is also ECC, and I this board doesn't support ECC. The manual states that , you will want unregistered or registered dual rank 1600 and install CPU 0 A1-16GB dual rank, B1-16GB dual rank, and CPU 1 A1-16GB dual rank, B1-16GB dual rank for the "best recommended performance" according to documentation and your 64GB installation goal.
 
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You mean CPU 0 2x16GB, and CPU 1 2x16GB....yes in second and fourth banks. It wont make anything less, unless according to the chart will make it less in performance. That is just the topology. Wow, looked up the DIMM and it was $40 beans o0! BUT, it is also ECC, and I this board doesn't support ECC. The manual states that , you will want unregistered or registered dual rank 1600 and install CPU 0 A1-16GB dual rank, B1-16GB dual rank, and CPU 1 A1-16GB dual rank, B1-16GB dual rank for the "best recommended performance" according to documentation and your 64GB installation goal.

yes that's a good deal just bought 4x16GB and this board does indeed support ECC, my current old, slow and faulty RAM memory does it, I've even enabled basic ECC check in the BIOS I thought it might help since I'm running vmware ESXi on it.
I suppose this RAM is DR right? I'm hoping to make it run at 1600MHz
 
Last edited:

Shikami

Gawd
Joined
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Messages
742
A motherboard, such as this one, will usually support ECC, but had no mention in the documents provided above. Still I looked up the manual to be sure, and on page 69: ECC mode. Yes, what I looked up about the DIMM/DRAM showed it to be dual rank (x4).
Here: https://www.samsung.com/semiconductor/dram/module/M393B2G70BH0-CK0/
and here: https://www.serversupply.com/MEMORY/PC3-12800/16GB/SAMSUNG/M393B2G70BH0-CK0Q9.htm.

According to the chart you should be good to go! Hopefully, and knowing Samsung you shouldn't have an issue with compatibility I believe. The compatibility lists are never extensive and only list two 1600 DIMMs.

Good luck and mention back if things are all good.
 
Joined
Sep 10, 2019
Messages
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A motherboard, such as this one, will usually support ECC, but had no mention in the documents provided above. Still I looked up the manual to be sure, and on page 69: ECC mode. Yes, what I looked up about the DIMM/DRAM showed it to be dual rank (x4).
Here: https://www.samsung.com/semiconductor/dram/module/M393B2G70BH0-CK0/
and here: https://www.serversupply.com/MEMORY/PC3-12800/16GB/SAMSUNG/M393B2G70BH0-CK0Q9.htm.

According to the chart you should be good to go! Hopefully, and knowing Samsung you shouldn't have an issue with compatibility I believe. The compatibility lists are never extensive and only list two 1600 DIMMs.

Good luck and mention back if things are all good.


Memory received but I won't be able to physically install until end of the month due to work travelling interference :-/
In the meantime I'm reading the Tyan manual in regarding memory configuration:
ftp://ftp1.tyan.com/doc/S8225_UG_v1.1.pdf

It seems like page 68 is the most relevant for RAM configuration. Any tip on how to set the following based on my 4x16GB modules?


Code:
Bank Interleaving
Bank Interleave setting has to do with the actual RAM chip properties, most good
quality RAM chips have "4-bank interleaving" and work best at this setting. Interleaving
controls how actual hits to memory takes place.
Enable Bank Memory Interleaving.
[Auto] / [Disabled]

Node Interleaving
Enable Node Memory Interleaving.
[Disabled] / [Enabled]

Channel Interleaving
Enable Channel Memory Interleaving.
[Auto] / [Disabled]

CS Sparing Enable
Reserve a spare memory rank in each node.
[Disabled] / [Enabled]

Bank Swizzle Mode
Enable or disable bank swizzle mode.
[Enabled] / [Disabled]
 

Shikami

Gawd
Joined
Apr 5, 2010
Messages
742
Bank Interleaving
[Auto]

Node Interleaving
Enable Node Memory Interleaving.
Your choice
I think these two links can allow you to choose because I do not know the processing in which you will want for your system: (https://hamelot.io/programming/the-importance-of-node-interleaving-on-amd-compute-nodes/) and within this page there is this link to this link coming. It describes if you are doing (physical) pCPU and (virtual) vCPU (https://frankdenneman.nl/2010/12/28/node-interleaving-enable-or-disable/) and how it will effect the DRAM access to nodes.

Channel Interleaving
Enable Channel Memory Interleaving.
[Auto]

CS Sparing Enable
Reserve a spare memory rank in each node.
[Disabled]

Bank Swizzle Mode
Enable or disable bank swizzle mode.
[Enabled]


Yeah, server boards configurations can be scary, and the manual is like, "pffft, you know. Auto, enable or disable and it will enable or disable the option."

Auto is enabled if the device is capable. The EFI and DRAM/device will configure with each other to operate. Bank and channel interleaving will occur as it does with x86 multi memory controllers (it is not a single controller anymore with a flat/monolithic space, its two or four, or more) . Node interleaving is very important for multi sockets and performance in particular circumstances. CS Sparing is more to do with failures and replacing memory and not important. Bank swizzle does a little remapping of DRAM with physical address bits to improve memory access and minimize the page conflicts.
 
Joined
Sep 10, 2019
Messages
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Bank Interleaving
[Auto]

Node Interleaving
Enable Node Memory Interleaving.
Your choice
I think these two links can allow you to choose because I do not know the processing in which you will want for your system: (https://hamelot.io/programming/the-importance-of-node-interleaving-on-amd-compute-nodes/) and within this page there is this link to this link coming. It describes if you are doing (physical) pCPU and (virtual) vCPU (https://frankdenneman.nl/2010/12/28/node-interleaving-enable-or-disable/) and how it will effect the DRAM access to nodes.

Channel Interleaving
Enable Channel Memory Interleaving.
[Auto]

CS Sparing Enable
Reserve a spare memory rank in each node.
[Disabled]

Bank Swizzle Mode
Enable or disable bank swizzle mode.
[Enabled]


Yeah, server boards configurations can be scary, and the manual is like, "pffft, you know. Auto, enable or disable and it will enable or disable the option."

Auto is enabled if the device is capable. The EFI and DRAM/device will configure with each other to operate. Bank and channel interleaving will occur as it does with x86 multi memory controllers (it is not a single controller anymore with a flat/monolithic space, its two or four, or more) . Node interleaving is very important for multi sockets and performance in particular circumstances. CS Sparing is more to do with failures and replacing memory and not important. Bank swizzle does a little remapping of DRAM with physical address bits to improve memory access and minimize the page conflicts.


Great input thanks and great also the link provided, incidentally I do run ESXi on top of this hardware so it's important to leave Node Interleaving off.
Just for me to fully understand this, what is that reference to SPDs on page 70 under DRAM Timing Config?
 

Shikami

Gawd
Joined
Apr 5, 2010
Messages
742
Just how you can configure the timings or make them even lower than capable. SPD is what you will want.
 
Joined
Sep 10, 2019
Messages
24
Many thanks for all the help here. I will definitely report back as soon as I can get the chance to install.
 
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