TSMC has taped out its first chip with limited use of extreme ultraviolet lithography (EUV) and will start risk production on a 5nm node with full EUV in April 2019. "TSMC said that N5 will deliver 14.7% to 17.7% speed gains and 1.8 to 1.86 area shrinks based on tests with Arm A72 cores. The N7+ node can deliver 6% to 12% less power and 20% better density; however, TSMC did not mention speed gains." Chip design tools for N5 aren't expected to be ready until November and some designs such as PCIe Gen 4 and USB 3.1 will have to wait until June. TSMC is offering two version of a planar 22-nm process that can compete with fully depleted silicon-on-insular processes from Globalfoundries and Samsung. "Some IP will not be available for the 22-nm nodes until June, including PCIe Gen 4, DDR4, LPDDR4, HDMI 2.1, and USB 3.1 blocks." TSMC is working with Cloud providers like Amazon Web Services and Microsoft to offer back-end chip design based in the cloud. TSMC used the cloud tools to design 5nm SRAM and Synopsys was successful with a tape out of a PCIe Gen 5 PHY block in TSMC's 7-nm node. Transistor density at N7 is 16.8x greater than at the foundry's 40-nm node, said TSMC. Unfortunately, costs are increasing, too. One source pegged total costs for an N5 design including labor and licensing at $200 to $250 million, up from $150 million for a 7-nm chip today, limiting pursuit of Moore's Law to the well-heeled. "We haven't tested all the possible combinations, but given that our PDKs are certified, we're confident in the service," said Suk Lee, a senior director of design infrastructure marketing at TSMC, noting that executives agreed to create the service just six months ago. "We did our N5 SRAM development in the cloud, and that speaks to how comfortable we are."