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TSMC Prepares "CoPoS": Next-Gen

erek

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“As demand for ever-growing AI compute power continues to rise and manufacturing advanced nodes becomes more difficult, packaging is undergoing its golden era of development. Today's advanced accelerators often rely on TSMC's CoWoS modules, which are built on wafer cuts measuring no more than 120 × 150 mm in size. In response to the need for more space, TSMC has unveiled plans for CoPoS, or "Chips on Panel on Substrate," which could expand substrate dimensions to 310 × 310 mm and beyond. By shifting from round wafers to rectangular panels, CoPoS offers more than five times the usable area. This extra surface makes it possible to integrate additional high-bandwidth memory stacks, multiple I/O chiplets and compute dies in a single package. It also brings panel-level packaging (PLP) to the fore. Unlike wafer-level packaging (WLP), PLP assembles components on large, rectangular panels, delivering higher throughput and lower cost per unit. Systems with PLP will be actually viable for production runs and allow faster iterations over WLP.”

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Source: https://www.techpowerup.com/337960/tsmc-prepares-copos-next-gen-310-x-310-mm-packages
 
I believe the price will be 40x too,
I think it is in part to save price.... AMD MI300x use that type of tech (the current CoWos) in some way more than Nvidia do with their GB200, without costing more for the customer.

In general rules the more monolithic you can be the better, but the more expensive it is

Could they just make a giant chips instead of many of them connected on a wafer (or now panel) they would.... seem to be some physical law or just too costly to go above ~850mm with the finest modern lithography.

at same yield, this should reduce cost to achieve the same performance (and the reason to do it), as the shape let you put more dies on the same area and being bigger let you put more dies as well and use simpler tools and substrate.
 
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