To all who trash conroe

[ToastMaster]

There's also an AMD is superior IMC and IPC myth. System #2 kicks the crap of out #1 when the games stop, hehehehe! Video Imressions, Creative's software, most of Roxio's and Nero's run faster and the AMD system gets killed multitasking. System #2 is the HTPC for that reason. System #2 is also setup for silent running and even under load with a Zalman 7K it stays about 48C with low fan speeds. This 55C with overclocked to 3.52 LOL!

Again, If Matel (they make Dolls) made what I needed processor wise I'd buy it.

AMD's IMC is superior though in terms of how the processor handles accessing memory, to how Conroe and others access memory. I'm pretty sure you won't find people debating that, except yourself.

The reason why Conroe, Yonah and others perform so well (and can equal that of the Athlon 64 series), is due to how the cores themselves are designed. Conroe especially is a SSE-monster (as it does SSE1/2/3 in a single cycle), with Micro-op and Macro- fusion, as well as the 4-issue wide core. The design is simply very, very powerful. Thus, as long as its fed the bandwidth in some form or another (and since it's via the FSB, it uses Smart Memory Access to mask the higher latency that comes along with the FSB/external memory controller).

I'd say that a external memory controller, with Smart Memory Access, is pretty close to being as good, but not quite as efficient or good, as a IMC.

 

[coldpower27]

Why or WHY doesn't Intel put an IMC?

Here are a few:

Intel has a chipset business which relies on different tiers of memory performance to differentiate it's products.

Intel since it make good chipsets won't benefit as much from moving to IMC like AMD did.

There is no need for the added complexity of the memory controller when you can keep it independent on the chipset.

You would need to move to a new Socket for each memory type change.

Intel is exceptional with cache desnities, with a large enough cache, the numbers of memory accesses is reduced.

Intel already will have the performance crown without the need to go to IMC.

You don't have memory flexibility and can't move to a new memory technology without a major overhaul of your infrastructure, you need to respin your processor and chipsets.

 

[coldpower27]

Thus, Conroe's 1066 FSB is already at the peak amount of bandwidth it can handle with DDRII 667 (which, infact, provides more bandwidth than the 1066 bus can use). I can see DDRII-800 becoming useful for Kentsfield, but I still feel like Kentsfield and Intel's other quadcore-based Conroe's are going to be bandwidth-deprived.

Edit- bandwidth deprived due to the FSB.

Yes and it also remains to be seen if 8.5GB/s of Bandwidth for Core Architecture is too little and constrain performance to the point it's uncompetitive. It may be an issue for Quad Core and it may not.

Take a look at Merom it has 333MHZ per Core and still it is 20% faster then Yonah which is itself about even to the equivalently clocked X2.

It's may have less bandwdith then AMD X4 will but does this mean the performance will suffer to the point where it is slower then X4, and that is the main point, if it still is beating it by 15-20% then it isn't a critical issue. To me High IPC architecture typically aren't starved for memory bandwidth, 1066FSB with 8.5GB/s is still plenty for a Quad Core.

I think people are seriously blowing the memory bandwidth issue out of the water for desktops, Xeon MP I can agree with you but not on the desktop.

 

[ToastMaster]

Yes and it also remains to be seen if 8.5GB/s of Bandwidth for Core Architecture is too little and constrain performance to the point it's uncompetitive. It may be an issue for Quad Core and it may not.

Take a look at Merom it has 333MHZ per Core and still it is 20% faster then Yonah which is itself about even to the equivalently clocked X2.

It's may have less bandwdith then AMD X4 will but does this mean the performance will suffer to the point where it is slower then X4, and that is the main point, if it still is beating it by 15-20% then it isn't a critical issue. To me High IPC architecture typically aren't starved for memory bandwidth, 1066FSB with 8.5GB/s is still plenty for a Quad Core.

I think people are seriously blowing the memory bandwidth issue out of the water for desktops, Xeon MP I can agree with you but not on the desktop.

That's why I usually say, we'll have to wait and see, and that it's just my own concern.

Also, remember that it doesn't really break down to a "333Mhz per core" idea. As most applications are not multi-threaded, usually it means that one core ultimately does the abundant share of the work. Thus, I don't each core shares the bus individually, but rather they work together to share both bus and cache, hence part of the Smart Memory Access technology.

My concern lies solely in how a twice as many course, sharing a slightly-faster bus, will perform when it comes to being able to have enough bandwidth. Remember, if a bandwidth bottleneck forms, there goes your performance.

That's why I think AMD's IMC and DDRII will prove very useful in the long-run as well, as it allows AMD to scale to quad cores without much concern for enough bandwidth being available.

And you're right, if there is a concern with this, it will effect the server line first, although as Intel moves quad-cores to desktop, it would start effecting that area as well.

 

[coldpower27]

That's why I usually say, we'll have to wait and see, and that it's just my own concern.

Also, remember that it doesn't really break down to a "333Mhz per core" idea. As most applications are not multi-threaded, usually it means that one core ultimately does the abundant share of the work. Thus, I don't each core shares the bus individually, but rather they work together to share both bus and cache, hence part of the Smart Memory Access technology.

My concern lies solely in how a twice as many course, sharing a slightly-faster bus, will perform when it comes to being able to have enough bandwidth. Remember, if a bandwidth bottleneck forms, there goes your performance.

That's why I think AMD's IMC and DDRII will prove very useful in the long-run as well, as it allows AMD to scale to quad cores without much concern for enough bandwidth being available.

And you're right, if there is a concern with this, it will effect the server line first, although as Intel moves quad-cores to desktop, it would start effecting that area as well.

And the critical word here is "IF" the bottleneck forms. No I think if most of the other cores are just idling away then the one core should have the bulk of the FSB to itself, similar to how one core can have all the cahce to itself when the other is not doing anything. My number is jsut that if the 4 cores were of equal load access the FSB all together at once.

The only reason why I think it may be an issue on Xeon MP's is because there you might have 2 buses for 4 Quad Cores.

1 Bus to 1 Quad Core to me is still fine.

 

[ToastMaster]

And the critical word here is "IF" the bottleneck forms. No I think if most of the other cores are just idling away then the one core should have the bulk of the FSB to itself, similar to how one core can have all the cahce to itself when the other is not doing anything. My number is jsut that if the 4 cores were of equal load access the FSB all together at once.

The only reason why I think it may be an issue on Xeon MP's is because there you might have 2 buses for 4 Quad Cores.

1 Bus to 1 Quad Core to me is still fine.

Yeah, I partly agree. I think that, considering most applications are single-threaded, and the fact that most people don't really multitask, it probably won't be much of an issue.

However, as more games are seriously multi-threaded, and people run more and more (for example, I'm often playing games and transcoding videos then burning them to DVDs at the same time) applications, it could then begin to become a problem. In my own view though, that could become an issue for either the shared bus, the shared cache, or possibly both.

It could also possibly be, that Intel did a great job designing both, and thus we won't see any problems. As you said, it's simply a giant "if", and we won't know for awhile. I certainly hope it doesn't occur.

 

[Donnie27]

Lol, not exactly, but close!

Oh brother, please make note of the meaning Joke LOL!

 

[enelson125]

Up until now all of the systems I have built have used AMD processors. I've only built 3 systems so far, but give me a break I'm a college freshman right now. I've been happy with AMD processors so far, being that they've been the best for gaming when I bought them. I thought I would always be an AMD user, but really my only motivation for choosing a CPU is performance and price.

It really looks like Intel has done well with Conroe and by all reports it will be a lot better than AMD's Socket AM2 processors. I am planning a system upgrade this summer/fall and I plan to choose whichever CPU is the best performer, and by the looks of it it will be a Conroe.

 

[Donnie27]

First of all, i820 and RAMBUS was not buggy at all. It was i820 + MTH + SDRAM that caused the problems. Get you facts straight please.

AMD's IMC is superior though in terms of how the processor handles accessing memory, to how Conroe and others access memory. I'm pretty sure you won't find people debating that, except yourself.

The reason why Conroe, Yonah and others perform so well (and can equal that of the Athlon 64 series), is due to how the cores themselves are designed. Conroe especially is a SSE-monster (as it does SSE1/2/3 in a single cycle), with Micro-op and Macro- fusion, as well as the 4-issue wide core. The design is simply very, very powerful. Thus, as long as its fed the bandwidth in some form or another (and since it's via the FSB, it uses Smart Memory Access to mask the higher latency that comes along with the FSB/external memory controller).

I'd say that a external memory controller, with Smart Memory Access, is pretty close to being as good, but not quite as efficient or good, as a IMC.

Most folks think it is useless to debate AMD folks who believe Hype more than reality. Before Conroe, AMD has an advantage, After Conroe, they don't=P

Latency is cut/saved by better prefetches made between the core's L1 and L2 Caches before they have a need to go the System RAM via SMA. Didn't you read the link? It's a 2 step system to Mask Latency of the External Memory Controller.

Both IMC and EMC have advantages and disadvantages, understanding that make some of this moot!

No, you're debating yourself. Then add to this your clear BIAS for AMD. AMD has NOTHING like Conroe's new SC or SMA unless you move to Dual Processors, not cores and use NUMA. On a single Dual Core Processor, that's not the case. Dothan/Yonah performs on Par with A64/X2 and Conroe SPANKS it=P That's not Intel BIAS that's what been seen so far. Shared Smart Cache between the two cores acts like NUMA on Conroe. You also don't have to repeat things I've already posted about Conroe with links.

As for Conroe's FSB, from Anandtech: "Intel also made it a point to mention that by the time Conroe ships DDR2-800 will be the memory of choice, however dual channel DDR2-667 already offers more memory bandwidth than Conroe’s 1066MHz FSB can use so the fact is meaningless."

I'll make it a point to say that's BS! One more time look up DMI on Intel's site? Or Anyone else reading this. Hint DMI stands for ____________________? DMA?

http://www.intel.com/design/chipsets/applnots/30146202.pdf

See section 2.1 titled Direct Media Interface?

http://www.anandtech.com/mb/showdoc.aspx?i=2681

So let's say there's 2 to 4GB of memory bandwidth more than the FSB to link to the Processor. PCI-E, I/O and etc..can Access that RAM Directly and Independently, even if the Processor bandwidth is Saturated=P It's the North Bridge CH Max speed that matters, NOT the Processor's link/FSB. PCI-E will take bandwidth when it talks to the Processor. It will take ZERO bandwidth when It independently needs to go to RAM if the Processor bus is saturated. Get it? They don't use a Single I/O HT link or etc..

You need to find the Max speed of the i975 and i965 or the North bridge CHIP itself. Its overall speed and bandwidth is what matters. It will or maybe should be faster than the Max speed of the Memory controller or the FSB to Processor, that's 1333MHz. Anand knows that and that's why some folks call them AMD Biased. Modern Chip Sets since the nForce2 have all did it this way in some form or another. Trying to say that the bandwidth is limited to the Processor's FSB is BOGUS.

Another example, remember CSI (Not the TV Show) on i8xx chip sets? The increased Bandwidth south of the North Bridge meant it was no longer needed when 915 Launched.

There's no way Intel, ATI, SIS, VIA and yes nVidia will support Intel Processors with DDR2-800 and NOT use a North bridge's Memory controller that can't account for that bandwidth=P

Conroe will have no bottlenecks to speak of=P Take about servers on the server forum "becouse" I don't have time, hehehe!

http://www.storagereview.com/guide2000/ref/hdd/if/ide/modesDMA.html

 

[visaris]

Trying to say that the bandwidth is limited to the Processor's FSB is BOGUS.

LOL! First you don't want to add AMD's mem bandwidth to their HT bandwidth, and now you want to do the equivalent for Intel's FSB (adding FSB bandwidth to DMA I/O bandwidth)! You frequently argue unfairly Donnie... Though, the point is well taken. You are correct that the total bandwidth of the system is greater than that of the FSB. I think it would be appropriate for me to update my numbers (all numbers are theoretical maximums):

Data bandwitdh in/out of the CPU:
* Yonah: 5.3GB/s
* Conroe: 8.4GB/s
* s939: 14.4 GB/s (8GB/s HT + 6.4GB/s RAM).
* AM2: 20.8GB/s (8GB/s HT + 12.8 GB/s RAM).
(IMHO these are the most important of the theoretical bandwidth numbers)

Total system bandwidth**:
* Yonah: 18.1GB/s ( 12.8GB/s I/O <-> RAM + 5.3GB/s I/O <-> CPU)
* Conroe: 21.2GB/s ( 12.8GB/s I/O <-> RAM + 8.4GB/s I/O <-> CPU)
* s939: 14.4 GB/s (8GB/s HT + 6.4GB/s RAM).
* AM2: 20.8GB/s (8GB/s HT + 12.8 GB/s RAM).
(IMHO these are interesting to think about, but don't mean a whole lot)

Though, total system bandwidth give us numbers which are theoretical in a major way because they reflect 8GB/s I/O + 12.8 GB/s RAM on the AM2 side, but 21.2GB/s of only I/O on the Conroe side. The only way to get Conroe's numbers up seems to stack the workload in a manner that is totally unrealistic. You see what I'm getting at here? The MCH helps improve bandwidth from I/O <-> RAM while an IMC helps improve bandwidth from CPU <-> RAM. Everyone here knows which one is more important, so I don't even need to bother mentioning it. Though, I guess I should give you credit for finding a way (no matter how unreasonable) to attach large numbers to the Conroe's bandwidth.

----

Conroe will have no bottlenecks to speak of.

There are only two ways this could possibly be true:
1) The Conroe cannot make use of more bandwidth than is provided by the FSB. -or-
2) The memory controller of the Conroe's platform never reaches an efficency such that there is more RAM bandwidth available than FSB bandwidth.

The two possibilities above are just food for thought; I'm not trying to make any specific claim here.

----

Again, I haven't (nor will I) comment on overall CPU performance. I'm just trying to keep the numbers as accurate and honest as possible throughout this discussion.

----

**:
Total system bandwidth defined by the quantity:
(I/O <-> RAM) + (I/O <-> CPU) + (CPU <-> RAM), where the data channels do not overlap. For example:

AM2 best case:
(I/O <-> CPU) + (CPU <-> RAM)

Conroe best case:
(I/O <-> RAM) + (I/O <-> CPU)

 

[ToastMaster]

First of all, i820 and RAMBUS was not buggy at all. It was i820 + MTH + SDRAM that caused the problems. Get you facts straight please.

Here's one link saying that the i820 issues were related to Rambus: Intel i820 update leaks

Now we move to another link saying basically the same: http://www.storagereview.com/articles/200111/20011109Renaissance_1.html

Now, it's well-known that the SDRAM-issues were related to the MTH, which ultimately was related due to trying to change Rambus memory protocols over so that SDRAM could be used. However, both those links point to bugs with the chipset using Rambus itself, not using SDRAM.

I think a Tom's quote from 2000 sums it up perfectly: "While the chip giant is still making billions and has thus certainly no serious reasons to complain about small profits or even losses, its reputation had to suffer rather badly. What had started with a buggy and therefore delayed 'Camino' (i820) chipset for the brand new 'Coppermine ' processor in Fall 1999, continued with the 'MTH-recall ".

There you have it - the chipset was buggy even before the MTH fiasco, partly explaining why it took so long to come out. Then, when they adopted the MTH to try and allow SDRAM to be used, even more problems came up.

So please Donnie, get *your* facts straight.

Most folks think it is useless to debate AMD folks who believe Hype more than reality. Before Conroe, AMD has an advantage, After Conroe, they don't=P

I'm technically a "AMD fok". I like AMD. Unlike yourself, I'm able to realize and thank AMD for what they've done in the past in terms of advancing processor technology.

That having been said, let's take a look to the past:

Athlon Classic > Pentium III.

Athlon Classic -> Athlon XP
Pentium III -> Pentium IV

Pentium IV (post-Willamette) > Athlon XP

Athlon XP -> Athlon 64

Athlon 64 > (generally) than Pentium 4.

Now we have:

Pentium 4/D -> Conroe

Conroe > Athlon 64

Notice a trend? That's how architecture cycles work. Any intelligent person will not be debating that Conroe is in fact better (in the benchmarks we've seen so far) than the K8 core-based systems. Then, in a year or two, I'm sure AMD will release an architecture that will "OMGWTFPWN" Conroe, and all the fence-sitters here who were praising Conroe and deriding AMD for having its ass handed to it, will then go "wow what will Intel do except price cuts" etc. Unfortunately, that's the way of the feeble.

Latency is cut/saved by better prefetches made between the core's L1 and L2 Caches before they have a need to go the System RAM via SMA. Didn't you read the link? It's a 2 step system to Mask Latency of the External Memory Controller.

Latency within the cache is saved because Intel has designed a better means of storing most-likely used operations. That's partly thanks to a larger cache size, and partly due to a more efficient means of storing what is likely to be used again. That is how cache truly works, and helps with operations.

Thus, because of this, it still can't mask a latency for a cache miss, because if it hasn't already stored the required information concerning a process that is being executed, than it is still going to have to go to main system ram to access it. That is where Smart Memory Access helps to reduce the latency as well, because it masks this call to the external ram. I'm guessing the improvement in cache is simply a better way of utilizing other operations, while either core accesses external memory.

Both IMC and EMC have advantages and disadvantages, understanding that make some of this moot!

You're right, they both do have advantages and disadvantages. However, to say the point is moot simply means you don't want to have to deal with it.

No, you're debating yourself. Then add to this your clear BIAS for AMD. AMD has NOTHING like Conroe's new SC or SMA unless you move to Dual Processors, not cores and use NUMA. On a single Dual Core Processor, that's not the case. Dothan/Yonah performs on Par with A64/X2 and Conroe SPANKS it=P That's not Intel BIAS that's what been seen so far. Shared Smart Cache between the two cores acts like NUMA on Conroe. You also don't have to repeat things I've already posted about Conroe with links.

First of all, I've always said that I'm a very large fan of AMD. However, as I've also said, that hasn't kept me from purchasing Intel processors. If you weren't cherry-picking my comments, you'd also have said about how I've praised Intel for Smart Memory Access and Smart Cache. It's a very powerful, good design.

Anyway, if you actually knew anything about the true workings of cache, especially with how the K8 cache subsystem works (and the fact that you don't know this, simply speaks for your dislike of AMD and all it does), you would know that the K8 is in some ways similar to how Conroe's Smart Cache works. From the sounds of it, Conroe know longer uses Intel's inclusive cache design, but instead opted for a exclusive cache design, which is helping to mask cache latencies. The K8 series also uses a exclusive cache design, although from what we've seen, Conroe's cache design is more efficient.

Also, Yonah is on par with an equivalent Athlon 64. I wouldn't say Dothan is...

Also, it isn't "shared smart cache". Smart Cache is the actual name for the design for how both cores share a singular cache. Thus, Smart Cache is singular in that sense.

Oh,and please, read up on NUMA. NUMA is in no way similar to Smart Cache, as NUMA is a means of allowing a processor to reduce the latency required to access external memory that is local to that core. It does not help to reduce latencies for accessing memory local to another core, nor the cache of that core (thus, it is generally in no way related to the technologies at work in Conroe).

For your benefit, I've included a link: NUMA

I'll make it a point to say that's BS! One more time look up DMI on Intel's site? Or Anyone else reading this. Hint DMI stands for ____________________? DMA?

http://www.intel.com/design/chipsets/applnots/30146202.pdf

See section 2.1 titled Direct Media Interface?

http://www.anandtech.com/mb/showdoc.aspx?i=2681

First of all, DMI is designed to reduce the bottleneck for bandwidth between individual components. This has *very little* to do with the available memory bandwidth directed towards the processor. We are discussing memory bandwidth available to the processor itself, not bandwidth between memory, the processor and other components, which is an entirerly different issue. Please, read up more on what a DMI truly does.

So let's say there's 2 to 4GB of memory bandwidth more than the FSB to link to the Processor. PCI-E, I/O and etc..can Access that RAM Directly and Independently, even if the Processor bandwidth is Saturated=P It's the North Bridge CH Max speed that matters, NOT the Processor's link/FSB. PCI-E will take bandwidth when it talks to the Processor. It will take ZERO bandwidth when It independently needs to go to RAM if the Processor bus is saturated. Get it? They don't use a Single I/O HT link or etc..

Ok, once again, you don't understand how a FSB works. The front side bus serves to operate at a given speed (in Conroe's case, 1066mhz). Now, it is at this speed that the total available bandwidth available to the processor, is transferred over. Now, the total amount of bandwidth that this bus can handle, depends upon the size and speed of the bus. Now, as we know from the Anandtech preview, we know that DDRII-667 is already providing more available bandwidth, than Conroe's FSB can actually make use of. This is at theoretical peak, and not even at what the real efficiency of the EMC is. Thus, the EMC takes all the total bandwidth, and delegates it out. Of this, a certain peak level of bandwidth is capable of being transferred over the 1066mhz bus. Apparently, DDRII-667 has more potential bandwidth for components to use, than Intel's EMC can make use of to funnel to the processor. The bus is this limit. If we were making use of a faster bus, more bandwidth could be used. Understand?

You need to find the Max speed of the i975 and i965 or the North bridge CHIP itself. Its overall speed and bandwidth is what matters. It will or maybe should be faster than the Max speed of the Memory controller or the FSB to Processor, that's 1333MHz. Anand knows that and that's why some folks call them AMD Biased. Modern Chip Sets since the nForce2 have all did it this way in some form or another. Trying to say that the bandwidth is limited to the Processor's FSB is BOGUS.

The bus speed of Kentsfield is 1333mhz. The bus speed, as stated by Intel for Conroe , is 1066 mhz. This is the speed at which Conroe will communicate with the Northbridge / memory controller. These numbers are in Intel's own press releases and information pages concerning Conroe. Is it really that hard to understand?

And yet, the available bandwidth is directly related to the processor's FSB, as it is this bus that funnels in bandwidth to the cores. What, do you think that bandwidth automatically just arrives from the northbridge to the cores using pixie dust?

[QUOTE}Another example, remember CSI (Not the TV Show) on i8xx chip sets? The increased Bandwidth south of the North Bridge meant it was no longer needed when 915 Launched.[/QUOTE]

CSI is the name for Intel's competing bus standard to that of Hypertransport. Of interest:
"In another development, Intel plans to embed a memory controller and to use a common high-speed serial interconnect as the processor bus for its Itanium and Xeon server processors starting in 2007, EE Times has learned. The so-called CSI interconnect will compete with HyperTransport, the fast, low-latency processor bus developed by AMD and used on its K8-class Opteron and Athlon processors. "

Hmm, embedded memory controllers for Itanium? Go figure.

There's no way Intel, ATI, SIS, VIA and yes nVidia will support Intel Processors with DDR2-800 and NOT use a North bridge's Memory controller that can't account for that bandwidth=P

Um, companies have in the past made use of faster memory, usually by designing their own (companies such as Via, SiS, etc.) memory controller. While it didn't always allow the processor itself to take advantage of the extra bandwidth, it would allow greater bandwidth for other components. Think back to the Athlon XP days, when it couldn't necessarily make use of the total available bandwidth of faster memory types, but it could make use of the actual increase in speed (and thus, a decrease partly in latency), and that's why companies would build chips around it.

We had a discussion awhile back concerning why Conroe would make use of DDRII-800 or faster versions later on, if it can't make use of the added bandwidth. Primarily, because it'll get a small performance increase from the faster ram. Thus, your idea is flat-out wrong.

Conroe will have no bottlenecks to speak of=P Take about servers on the server forum "becouse" I don't have time, hehehe!

So basically, what you're saying is, even though Intel, and sites such as Anandtech have stated that more bandwidth is provided by DDRII-667 than Conroe can handle, that all of these people (including Intel itself) is wrong, and that you, oh great Donnie, are right? That Conroe will *obviously* have no concerns with its bandwidth. Yes, I'm certain to believe that...

And the whole reason we're discussing Conroe and bottlenecking of the bandwidth here is not due to server-talk (although that was included), but because of this nice little chip called Kentsfield. Maybe you've heard of it? A Desktop processor, Quad-core, using a 1333 bus. Based off of Conroe. See that key word? *Desktop*. We're discussing bottlenecking, because of our concern for how this *desktop* processor will perform, using quad cores on a slightly faster bus. Don't blame me because you selectively read.

 

[ToastMaster]

Visaris, Intel has already stated that DDRII-667 provides more bandwidth, than the EMC can fully make use of for the 1066 mhz FSB. This was reported on by Anandtech and others, in their IDF Conroe previews.

Thus, the only advantage DDRII-800 brings is a faster memory speed, but no actual bandwidth improvements for the processor itself.

I don't know if Conroe itself is limited to how much bandwidth its using, or if it's simply a issue with the FSB. If it's Conroe, than right now it's pretty much peaked. If it's the FSB (as I honestly suspect), than Conroe will be even more impressive when the time comes (atleast, in terms of bandwidth usage).

 

[Donnie27]

LOL! First you don't want to add AMD's mem bandwidth to their HT bandwidth, bla bla bla

Conroe kicks ass and it's Conroe or bust!

 

[visaris]

LOL! First you don't want to add AMD's mem bandwidth to their HT bandwidth, bla bla blaQUOTE]

Conroe kicks ass and it's Conroe or bust!

LOL!

 

[Donnie27]

Visaris, Intel has already stated that DDRII-667 provides more bandwidth, than the EMC can fully make use of for the 1066 mhz FSB. This was reported on by Anandtech and others, in their IDF Conroe previews.

Thus, the only advantage DDRII-800 brings is a faster memory speed, but no actual bandwidth improvements for the processor itself.

I don't know if Conroe itself is limited to how much bandwidth its using, or if it's simply a issue with the FSB. If it's Conroe, than right now it's pretty much peaked. If it's the FSB (as I honestly suspect), than Conroe will be even more impressive when the time comes (atleast, in terms of bandwidth usage).

Link please? Intel already stated on my link that it will support PC-800.

 

[ToastMaster]

LOL!

Yeah, I must admit, I laughed well at that too.

 

[Donnie27]

LOL!

July Dewd, July

 

[ToastMaster]

Link please? Intel already stated on my link that it will support PC-800.

Yeah. I said myself, Intel will support DDRII-800. In the IDF announcement, Intel said it would support DDRII-800.

However, that doesn't change the fact that DDRII-800 won't help it except for a slight performance increase over DDRII-667, due purely to the faster memory speed. Conroe can't make use of the additional bandwidth it provides, as DDRII-667 already provides more than enough.

 

[ToastMaster]

July Dewd, July

Well, until July... X2 kicks ass! X2 or bust!

 

[pxc]

First of all, DMI is designed to reduce the bottleneck for bandwidth between individual components. This has *very little* to do with the available memory bandwidth directed towards the processor. We are discussing memory bandwidth available to the processor itself, not bandwidth between memory, the processor and other components, which is an entirerly different issue. Please, read up more on what a DMI truly does.

DMI is very applicable when describing why anyone would want memory with more bandwidth than necessary for the CPU alone.

Devices like hard drives, PCI masters (including USB) and PCI-Express cards can access memory directly without the CPU. It doesn't change overall performance much with current desktop applications, but there are cases where increasing memory bandwidth helps with I/O bound devices. You could argue for different ways in achieving that and I might not disagree.

Well, until July... X2 kicks ass! X2 or bust!

I plan on buying a Conroe CPU and board for my next upgrade, but I am excited to see what a 65nm 35W desktop X2 3800+ is capable of.

 

[Donnie27]

Well, until July... X2 kicks ass! X2 or bust!

Hahahaha!

 

[Donnie27]

DMI is very applicable when describing why anyone would want memory with more bandwidth than necessary for the CPU alone.

Devices like hard drives, PCI masters (including USB) and PCI-Express cards can access memory directly without the CPU. It doesn't change overall performance much with current desktop applications, but there are cases where increasing memory bandwidth helps with I/O bound devices. You could argue for different ways in achieving that and I might not disagree.

I plan on buying a Conroe CPU and board for my next upgrade, but I am excited to see what a 65nm 35W desktop X2 3800+ is capable of.

He knows that's the case, he's just Troll baiting.

 

[Donnie27]

Ok, once again, you don't understand how a FSB works. The front side bus serves to operate at a given speed (in Conroe's case, 1066mhz). Now, it is at this speed that the total available bandwidth available to the processor, is transferred over. Now, the total amount of bandwidth that this bus can handle, depends upon the size and speed of the bus. Now, as we know from the Anandtech preview, we know that DDRII-667 is already providing more available bandwidth, than Conroe's FSB can actually make use of. This is at theoretical peak, and not even at what the real efficiency of the EMC is. Thus, the EMC takes all the total bandwidth, and delegates it out. Of this, a certain peak level of bandwidth is capable of being transferred over the 1066mhz bus. Apparently, DDRII-667 has more potential bandwidth for components to use, than Intel's EMC can make use of to funnel to the processor. The bus is this limit. If we were making use of a faster bus, more bandwidth could be used. Understand?

Ok, once again, you don't understand how a FSB works as it realates to current chip sets.

 

[ToastMaster]

He knows that's the case, he's just Troll baiting.

Um no, i'm simply generally correcting your mistakes.

 

[Donnie27]

Um no, i'm simply generally correcting your mistakes.

Yeah, I made no mistakes! You need to read up on Current Chipsets and then you'll see plenty you made. According to you, Chip Set FSB to RAM Ratios don't work, right? On your Intel system set your Ratio and to 4:5. Then explain what happens?

 

[ToastMaster]

Ok, once again, you don't understand how a FSB works as it realates to current chip sets.

No, I do. I've been following FSB development for over a decade.

Let's see. Intel's current designs:

Processor -> External Memory Controller (Part of the Northbridge)

Now Donnie, what connects the processor to the external memory controller? Oh wait, that's right, the front side bus.

"Current usage

Most modern buses (both GTL+ and EV6 from DEC Alpha) serve as a backbone between the CPU and a chipset. This chipset (usually a combination of northbridge and southbridge) is the connection point for all other buses in the system. The PCI, AGP, and memory buses all connect to the chipset to allow for data to flow between the connected devices."

and

"CPU

The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front side bus (FSB) speed. For example, a processor running at 550 MHz might be using a 100 MHz FSB. This means there is an internal clock multiplier setting of 5.5; the CPU is set to run at 5.5 times frequency of the front side bus: 100 MHz x 5.5 = 550 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved."

Now, some FSB numbers:

Intel Core* 133/166 MHz 4266/5333 MB/s

with Core pumping information information at 4 times per cycle

For reference:

Pentium M* 100/133 MHz 3200/4266 MB/s

Pentium D* 133/200 MHz 4266/6400 MB/s

What determines bandwidth, at these speeds, is at what rate the processor can take in data per number of times per cycle (hence why Yonah, Dothan, etc. transferring at 4 times per cycle).

This is unchangeable, without a architecture redesign.

As you increase the bus speed, the amount of data input to the processor increases per cycle, as you're carrying more data along the bus. However, simply changing the type of memory used, will not effect bandwidth, unless the memory itself is the bottleneck to the system.

Now we know that at Conroe's current FSB, DDRII-667 is more than adequate. Thus, moving to DDRII-800 will only result in a slight performance increase due to the actual speed of the ram itself. The FSB however for Conroe is locked at 1066mhz, and thus can't make use of any additional bandwidth that is provided.

Kentsfield, the quad-core version of Conroe (in reality, Kentsfield is a slightly cut-down version of Conroe), will make use of a 1333mhz FSB. This means that it'll have more bandwidth available, and thus DDRII-800 makes more sense.

That is why many people state that, in terms of accessing bandwidth, an IMC is more efficient. It's not limited to a bus speed, and thus runs at the full speed of the processor. The major drawback, and likely the largest reason why Intel doesn't use one, is because once you essentially peak at efficiency for bandwidth, and you have designs that are going to require more (aka quad cores), you'll have to move to a new memory type that can provide the required bandwidth. This then means designing a new IMC, such as what AMD did with AM2. Thus, it's easier to simply replace the north bridge with one that allows for an alternative memory type.

Understand? I can link you to many, many articles concerning basic bus concept and design. It's really not that complicated of an idea...

 

[ToastMaster]

Yeah, I made no mistakes! You need to read up on Current Chipsets and then you'll see plenty you made. According to you, Chip Set FSB to RAM Ratios don't work, right? On your Intel system set your Ratio and to 4:5. Then explain what happens?

No, I never said that. Now you're simply putting words in my mouth.

The aspect ratio between a FSB and the processor, determines at what speed a processor can run.

This is where overclocking comes in, and why people spend so much on the best available ram, that they know can operate at speeds above listed spec.

You increase processor speed and the speed of the fsb. Now, your processor is able to utilize more potential bandwidth, and thus a ram capable of delivering it, as well as operating at that speed, is rquired.

However, stock Conroe's run at 1066mhz. At this speed, DDRII-667 provides more bandwidth than Conroe's FSB can make use of. We have numerous comments confirming this. Is it really that hard to understand?

You can throw DDRII-1066 into it, and Conroe still won't be able to take advantage of it. Why? Because the FSB itself is limited to how much potential bandwidth it can carry.

Geez, I didn't realize it was that complicated...

 

[ToastMaster]

And all a chipset determines, is how it makes use of that FSB.

Thus, for your PIII and Athlon Classic designs, the memory controller in the chipset was single-channel, single cycle.

Then, as time went by, processors came along that supported a quad transfer of data per cycle, hence how FSB were "quad pumped".

So the FSB is related to the chipset, in how the chipset is able to handle data transfer per cycle on the bus. If you honestly think it's any other way than this, you're smoking some rather nice stuff.

Conroe, at the moment, is likely having a quad transfer of data per cycle, similar to Yonah, Dothan, the P4s, etc. Thus, the only thing that can increase the amount of available bandwidth, is increasing the FSB, so that more data is able to be input, via whater number of data transfers, per cycle. Simply changing from DDRII-667 to DDRII-800 will not in any way effect available bandwidth, as Conroe's FSB is already handling as much as it can (although we don't know the efficiency).

 

[ToastMaster]

DMI is very applicable when describing why anyone would want memory with more bandwidth than necessary for the CPU alone.

Devices like hard drives, PCI masters (including USB) and PCI-Express cards can access memory directly without the CPU. It doesn't change overall performance much with current desktop applications, but there are cases where increasing memory bandwidth helps with I/O bound devices. You could argue for different ways in achieving that and I might not disagree.

I also never stated that there is no reason for increasing the available bandwidth from memory beyond what the FSB can handle. What I said (or atleast, I meant to state), was that there as no point in changing to a faster, more bandwidth-providing ram such as DDRII-800 if your intent is to attempt to increase the bandwidth available to the processor itself, at stock speeds.

however, he was trying to relate DMI to increasing performance of the processor itself, by providing it with more bandwidth. That is why I was shooting down his idea of DMI.

plan on buying a Conroe CPU and board for my next upgrade, but I am excited to see what a 65nm 35W desktop X2 3800+ is capable of.

As am I (concerning Conroe), although I'll also be picking up a lower-powered X2 4800+ for my back-up system.

 

[Donnie27]

I also never stated that there is no reason for increasing the available bandwidth from memory beyond what the FSB can handle. What I said (or atleast, I meant to state), was that there as no point in changing to a faster, more bandwidth-providing ram such as DDRII-800 if your intent is to attempt to increase the bandwidth available to the processor itself, at stock speeds.

however, he was trying to relate DMI to increasing performance of the processor itself, by providing it with more bandwidth. That is why I was shooting down his idea of DMI.

As am I (concerning Conroe), although I'll also be picking up a lower-powered X2 4800+ for my back-up system.

You're just digging a Deeper hole. I said system, nothing about Processor performance.

I said, DMI and DMA can acess the bandwidth over and above the FSB to the Processor. That extra bandwidth can be used by the system. Everyone knows the processor can't use more than its FSB allows. Yet you said the memory Controller couldn't what?

Visaris, Intel has already stated that DDRII-667 provides more bandwidth, than the EMC can fully make use of for the 1066 mhz FSB. This was reported on by Anandtech and others, in their IDF Conroe previews.

Anand was WRONG on that one. Hell even the PCI-E can use memory independent of the Processor.

I simply asked for a Link because even Visaris didn't correct this BooBoo either! Intel's EMC can support whatever RAM its set up for=P If that's DDR2 800MHz then its supported=P The Processor would use 667MHz of it and the system could access some of the other independant of the Processor.

Please don't try to pretend to explain the FSB to me, that's silly. You still don't get how Intel's HUB architecture works.

There are links within the Hub that links; Processor-->FSB-->Hub-->EMC. Then there's PCI-E-->Link-->HUB, DMI-->Link-->HUB and once at the HUB, data can go to the FSB or STRAIGHT to the EMC from its Hub links=P That's the simple version, not counting buffers, ECC and etc.. These devices are NOT riding one FSB as you said. If Intel gives the Controller DDR2 Dual Channel support for DDR2 1200, then that will more than likely be the top speed or Top Data rate of that Hub Controller. The Top speed has to be at least as fast as the fastet device. Maybe if I said Intel's Intel's North Bridge Memory Controller Hub works similar to nVidia's Crossbar, maybe you'd get it?

Now we know that at Conroe's current FSB, DDRII-667 is more than adequate. Thus, moving to DDRII-800 will only result in a slight performance increase due to the actual speed of the ram itself. The FSB however for Conroe is locked at 1066mhz, and thus can't make use of any additional bandwidth that is provided.

I said the Sub Systems can make use of the extra bandwidth. This could improve System permance, like adding a better HDD. You said they couldn't, just at least admit you're wrong? I say again, additional bandwidth can be used by DMA, PCI-E and DMI (DMI covers all I/O traffic).

If the Processor is saturating the Memory bandwidth 100%, without the extra bandwidth, then just as any TRUE Hub 1:1 anything needing some has to steal that bandwidth from the Processor. Now if the Processor was saturating 8.4GB of 10.8GB those systems would go to the Extra Bandwidth, empty memory, first. Not take it from the FSB or the Processor until all 10.8GB is used.

Now I hope that helps you?

Its not just this one thing, I linked to MTH and errata doesn't show itself on any of the old i820 I still see folks using. No, X2 only wishes it was kicking 9xx Presler's ass like Conroe kicked its ass LOL!

 

[duby229]

I said, DMI and DMA can acess the bandwidth over and above the FSB to the Processor. That extra bandwidth can be used by the system. Everyone knows the processor can't use more than its FSB allows. Yet you said the memory Controller couldn't what?

It goes back to that old saying "The truth, the whole truth, and nothing but the truth"

What you say is true, but it isnt the whole truth. You fail to take into account interupts and so on, which still to this day account for quite a bit of bandwidth. There are still others as well. PCI, and hence forth also PCIe addresses need to be addressed byt the CPU, and just a ton of other things as well. It goes a lot deeper then I can explain. That is the bottleneck.

Anand was WRONG on that one. Hell even the PCI-E can use memory independent of the Processor.


That is just the thing, with DDR2-800
I simply asked for a Link because even Visaris didn't correct this BooBoo either! Intel's EMC can support whatever RAM its set up for=P If that's DDR2 800MHz then its supported=P The Processor would use 667MHz of it and the system could access some of the other independant of the Processor.

Please don't try to pretend to explain the FSB to me, that's silly. You still don't get how Intel's HUB architecture works.

His explaination was spot on. What I think that what some people fail to realize is that memory addressing must be done by the CPU. No matter what device has that memory allocated. AMD uses something called an IOMMU, which to my knowledge has no equivalent in an Intel architecture, which means that all IO requests must be handled by the CPU.

So If all Intel can use is DDR2-667, that it doesnt matter if the chjipset supports DDR2-800, it will be bottlenecked at lowerbandwidths.

I said the Sub Systems can make use of the extra bandwidth. This could improve System permance, like adding a better HDD. You said they couldn't, just at least admit you're wrong? I say again, additional bandwidth can be used by DMA, PCI-E and DMI (DMI covers all I/O traffic).

If the Processor is saturating the Memory bandwidth 100%, without the extra bandwidth, then just as any TRUE Hub 1:1 anything needing some has to steal that bandwidth from the Processor. Now if the Processor was saturating 8.4GB of 10.8GB those systems would go to the Extra Bandwidth, empty memory, first. Not take it from the FSB or the Processor until all 10.8GB is used.

That is what he was trying to say. DDR2-667 will saturate the FSB bandwidth. Therefore anything faster then that is simply wasted. It really doesnt matter if the chipset supports faster memory. All IO requests are serviced by the CPU anyway, so all that extra memory bandwidth is being wasted.

Intel is in the same situation that the nForce 2, and Athlon XP was several years ago. The chipset provides mor memory bandwidth, then the FSB can funnel to the CPU, and it is beingwasted.

 

[$BangforThe$]

Duby 229 why are you trolling Intel conroe.

I was just readying old post in the Intel Conroe threads. You talk about Whole truth!

Here's what you have stated in some threads.

1). Waffer die yields on Conroe!! You said less than 50%
2). Conroe performance!! You said hand picked secret not real conroe's
3) Conroe release!! You said Aug. Sept. low availability.
4) Conroe 3.33GHz. EE You said noway.

Really I don't care what you say but wouldn't it be better said in the AMD forum instead of Intel forum where you and I both know good Intel fans would hang. Intel form is OK but a few links that backup some of what you say would be nice. The way your doing it just seems like flamebate.

 

[finalgt]

Conroe is impressive performance, no doubt about that, but I STILL do not understand why people will get excited over engineering samples. Somehow I doubt all of the retail CPUs will be hitting 3.3ghz on stock cooling...but I could be wrong.

 

[duby229]

Duby 229 why are you trolling Intel conroe.

I was just readying old post in the Intel Conroe threads. You talk about Whole truth!

Here's what you have stated in some threads.

1). Waffer die yields on Conroe!! You said less than 50%
2). Conroe performance!! You said hand picked secret not real conroe's
3) Conroe release!! You said Aug. Sept. low availability.
4) Conroe 3.33GHz. EE You said noway.

Really I don't care what you say but wouldn't it be better said in the AMD forum instead of Intel forum where you and I both know good Intel fans would hang. Intel form is OK but a few links that backup some of what you say would be nice. The way your doing it just seems like flamebate.

All of it is based on info that is freely available.

Besides. I see you post in the AMD forum sometimes too. I don't flame Intel, the same as you don't flame AMD. I see information that is incorrect, or incomplete, I offer an alternative opinion. Thats what forums are for. Discussion.

I never said Intel sucks. I never said Conroe sucks. I think Intel is a great company. I think Conroe will be a great chip.

But the fact is that misinformation is misinformation no matter what forum it is being posted in. I am just simply offering an educated alternative.

From the very beginning I said we should wait it out and see with REAL hardware. Based on information that was available at the time I said that August would be a reasonable launch time, that has since changed. Good for Intel I say. The sooner, the better. Based on freely available information Intel yeilds at 65nm suck less then 50% I assume this is the same or worse for Conroe, being thta it is a new die. I know it will get better, and it prolly already is better. The best OC right now is 3.1GHz I think it is pretty reasonable that a factory clock of 3.33GHz wont come out anytime soon.

It is called logic. It is called research. It is called education.

You see some people to choose to see what they want to see. And hear what they want to hear. Beleive what they want to beleive. But what they percieve is an illusion. Some people call that illusion FUD.

 

[visaris]

It is called logic. It is called research. It is called education.

QFT

 

[coldpower27]

Based on freely available information Intel yeilds at 65nm suck less then 50% I assume this is the same or worse for Conroe, being thta it is a new die.

Freely available information that Intel has lower then 50% yield? Where a link a please? Either that or just complete BS. There is no way I will accept yeild numbers from just anybody on the net without the linkage necessary to back it up. Considering Intel and AMD yield information are trade secrets and closely guarded. I find your claims questionable at best.

And I remember asking you for this information before and still you have yet to provide it.

 

[coldpower27]

The best OC right now is 3.1GHz I think it is pretty reasonable that a factory clock of 3.33GHz wont come out anytime soon.

1 perspective on the issue.

It takes about 1.55GHZ FSB to get to 3.1GHZ using the x8 multiplier of the 2.13GHZ ES Conroe chip, so the bottleneck could easily be the FSB instead of headroom of the chip itself.

This is also on ES of the chip, actual retail models typically have better headroom as the core is improved over time.

 

[ToastMaster]

You're just digging a Deeper hole. I said system, nothing about Processor performance.

I said, DMI and DMA can acess the bandwidth over and above the FSB to the Processor. That extra bandwidth can be used by the system. Everyone knows the processor can't use more than its FSB allows. Yet you said the memory Controller couldn't what?

No, all you said, concerning DMI and DMA, was a simple statement of "Do you know what DMI and DMA stand for, and then you posted a couple of links, in regards to my comment concerning the amount of bandwidth for Conroe over the FSB (aka, between the processor and the northbridge). Thus, it is *you* who posted irrelevant information.

Anand was WRONG on that one. Hell even the PCI-E can use memory independent of the Processor.

No, Anand was right. All he stated was that at the moment, DDRII-667 provides a total available amount of bandwidth that is higher, than what Conroe's FSB can actually make use of, directed between the northbridge and the processor. If you can't grasp that, I'm sorry. It's pretty simple...

I simply asked for a Link because even Visaris didn't correct this BooBoo either! Intel's EMC can support whatever RAM its set up for=P If that's DDR2 800MHz then its supported=P The Processor would use 667MHz of it and the system could access some of the other independant of the Processor.

First of all, your comment concerning "the processor would use 667mhz of it" is pure nonsense. That's the speed of the memory itself! At 667mhz, DDR II can provide a certain amount of bandwidth. Some does go to the system outside of the FSB, your right. However, for what is available for the FSB itself to use, there is more available than what Intel's FSB can support. Intel's EMC supports DDRII-800 because a) they'll be moving relatively quicker to faster FSBs, in which case it'll be able to make use of the extra bandwidth for between the northbridge/EMC and the processor, b) it provides more total bandwidth for the system as a whole, and c) as it's faster, it will give a very slight performance increase for Conroe. Understand? Noone ever said Intel's EMC wasn't going to support DDRII-800, so I don't know where you got that crazy idea from.

Please don't try to pretend to explain the FSB to me, that's silly. You still don't get how Intel's HUB architecture works.

There are links within the Hub that links; Processor-->FSB-->Hub-->EMC. Then there's PCI-E-->Link-->HUB, DMI-->Link-->HUB and once at the HUB, data can go to the FSB or STRAIGHT to the EMC from its Hub links=P That's the simple version, not counting buffers, ECC and etc.. These devices are NOT riding one FSB as you said. If Intel gives the Controller DDR2 Dual Channel support for DDR2 1200, then that will more than likely be the top speed or Top Data rate of that Hub Controller. The Top speed has to be at least as fast as the fastet device. Maybe if I said Intel's Intel's North Bridge Memory Controller Hub works similar to nVidia's Crossbar, maybe you'd get it

No, I know how the HUB works. However, it's you who doesn't understand the very simpleness of it all.

You yourself above pointed to how the FSB is important in the grand scheme of things. Let's see: Processor -> FSB -> HUB -> EMC. However, I'd like to point out one little flaw in your definition: the EMC ultimately *is" the "HUB" (well, Intel considers the northbridge the HUB, and the EMC is a part of the northbridge, and thus is also the "HUB"), per Intel's own definition: "Their north bridge chips—or memory controller hubs (MCH), as Intel likes to call them—include a PCI Express X16 interface for graphics, replacing AGP, and a new memory controller capable of working with DDR2 memory."

Thus, you're idea above is completely irrelevant, since you're entirerly confused on what the actual definition of the HUB is.

However, I will once again explain it in hopefully simplistic terms, so you maybe *finally* can grasp it:

A Processor wants to connect to External Memory Controller (EMC). Thus, in order to allow for this communication, the front side bus is put into place. Now the processor is capable of running this front side bus at a certain speed, per the speed designed by those who design the processor. In Conroe's case, it runs at 1066mhz. That means, that at 1066mhz, a certain level of bandwidth can be transfered between Conroe, and the external memory controller. Now this is blind to the actual speed of the ram. All that matters, is that this total amount of bandwidth, is being delivered. Thus, it can be DDRII-667, DDRII-800, whatever, as long as that bandwidth is there. However, because the bus only runs at 1066mhz, whatever this level of bandwidth is, will be unchanging. Until you actually increase the FSB bus, this bandwidth total is set. Thus, if DDRII-667 is already providing more bandwidth than this bus is able to fully use, the rest of the bandwidth is available for the rest of the system and if the system can't make use of all of it, than it doesn't get used. Now, if DDRII-800 is implemented, it'll increase the total amount of bandwidth available to the system. However, this is not reflected in an increase of bandwidth to the processor because, as we've already established above, the 1066mhz FSB cannot make use of it.

Now, if Intel were to move this FSB up to 1333mhz, then yes, we could make use of additional bandwidth. However, for the moment, that isn't occuring, so it's stuck with what's available.

DDRII-800 will slightly increase performance thanks to the faster speed of the ram itself, as we've decided. Ultimately however, that's it.

I said the Sub Systems can make use of the extra bandwidth. This could improve System permance, like adding a better HDD. You said they couldn't, just at least admit you're wrong? I say again, additional bandwidth can be used by DMA, PCI-E and DMI (DMI covers all I/O traffic).

I never said anything of the like. You're putting words in my mouth, so please inform me to where I said the system couldn't make use of the additional bandwidth.

What I said, is that DMI/DMA and the bandwidth for these, had ultimately on effect on the link between the processor and the EMC. This is true. Others have confirmed it. Look it up online, and that will confirm it.

Also, look at it this way: HDDs, even SATA II, aren't even using half the total possible bandwidth and transfer rate generally that is available. Thus, your analogy is pointless.

If the Processor is saturating the Memory bandwidth 100%, without the extra bandwidth, then just as any TRUE Hub 1:1 anything needing some has to steal that bandwidth from the Processor. Now if the Processor was saturating 8.4GB of 10.8GB those systems would go to the Extra Bandwidth, empty memory, first. Not take it from the FSB or the Processor until all 10.8GB is used.

Now I hope that helps you?

WTF are you smoking? A processor doesn't "saturate" memory bandwidth. Generally, when you are carrying out an operation, the processor will make use of whatever bandwidth is required to run what is needed. Under intense situations, that bandwidth might be fully made use of. However, as we've seen, no memory controller is 100% efficient. Also, the memory controller delegates out bandwidth to all parts of the system. However, in general, it will always make sure that the processor is making use of as much bandwidth as it requires. Also, you generally have more bandwidth available now, than the system can fully make use of. Thus, there is no problem. Understand?

Its not just this one thing, I linked to MTH and errata doesn't show itself on any of the old i820 I still see folks using. No, X2 only wishes it was kicking 9xx Presler's ass like Conroe kicked its ass LOL!

Ok, let's look at any benchmarks, and I'm pretty certain that at all stock speeds, X2 still holds advantages easily over Presler. Noone ever said that the performance difference was equal to the difference between Conroe and the K8 series. You truly are smoking some great shit.

 

[coldpower27]

Ok, let's look at any benchmarks, and I'm pretty certain that at all stock speeds, X2 still holds advantages easily over Presler. Noone ever said that the performance difference was equal to the difference between Conroe and the K8 series. You truly are smoking some great shit.

Well the situations is quite a bit better for Intel now, as the Pentium D 950 now competes with the Athlon 64x2 3800+. The rest of the Pentium D line worth caring about has no competitor from the Athlon 64x2 line.

That is the only possible comparison you can make for the Pentium D line, the rest of the models are cheaper.

I wolud still say the Athlon FX 60 hold a advantage over Pentium EE 965 though.

 

[Donnie27]

Its not just this one thing, I linked to MTH and errata doesn't show itself on any of the old i820 I still see folks using. No, X2 only wishes it was kicking 9xx Presler's ass like Conroe kicked its ass LOL!

Ok, let's look at any benchmarks, and I'm pretty certain that at all stock speeds, X2 still holds advantages easily over Presler. Noone ever said that the performance difference was equal to the difference between Conroe and the K8 series. You truly are smoking some great shit.

LMFAO!

X2s of any kind don't come close to putting the ass whoopin on Penitum D that Conroe lays down on it=P

The North Bridge and Hub architecture came up because you took what Anand said about Conroe as a Fact when it is NOT. Doesn't take a long assed post kill that one.