SPD/EPP help, getting it right?

[CoW]8(0)]

Memory type:			DDR2 SDRAM
Error correction:			NONE
Voltage interface level:		SSTL (1.8V)
Data width:			64 bits
Number of physical banks:		2 (double sided)
Number of logical banks:		4
Number of row addresses:		14       14
Number of col addresses:		10       10
Bank density:			512	 512 MB
Primary RAM Width:		8        8 bits
Error checking RAM Width:		0        0 bits
Module density:			1024 MB
Refresh rate:			7812.500 us
Self-refresh:			Yes
Burst lengths supported:		 	 4 8 	
CAS 4.0:   
	Cycle time (tCYC) =    3.000 ns	fMax =  333.333 Mhz
	Access time (tAC) =    0.450 ns	fMax = 2222.222 MHz
CAS 5.0:   
	Cycle time (tCYC) =    2.500 ns	fMax =  400.000 Mhz
	Access time (tAC) =    0.400 ns	fMax = 2500.000 MHz
Not reportedNot reportedMin delay, Bk/Bk random cols:	0 clocks
Min row precharge time (tRP):	12.500   ns
Min row active delay (tRRD):		7.500    ns
Min RAS to CAS delay (tRCD):	12.500   ns
Min Actv to precharge (tRAS):	45.000   ns
Addr/Cmd setup time:		0.170    ns
Addr/Cmd hold time:		0.250    ns
Data setup time:			0.050    ns
Data hold time:			0.120    ns
Write recovery time (tWR)		15.000   ns
Int Wr to Rd Cmd Dly (tWTR)		7.500    ns
Int Rd to Pchg Cmd Dly (tRTP)	7.500    ns
Min Act/Auto-Rfrsh Time (tRC)	57.500   ns
Min Auto-Rfrsh/Act Cmd (tRFC)	105.000  ns
Max Dev Cycle time (tCK max)	8.000    ns
Max DQS-DQ Skew (tDQSQ max)	2.000    ns
Rd data hold skew Fctr (tQHS)	3.000    ns
PLL relock time			0.000    ns
Memory analysis probe chars:		00
DIMM type:                   UDIMM (module width = 133.35mm)
FET switch external enable:		No
Analysis probe installed:		No
Includes weak driver:		Yes

Module manufacturing location:	0 (manufacture dependant)
Module part number:		                  
Module revision code:		0 (manufacture dependant)
Module manufacturing date:		Not reported

SPD revision:			1.1

--- NVIDIA Enhanced Performance Profile SPD information ---

SPD version:			B1
Profile for Optimal Performance:	01

Profile 0 valid
Voltage Level:			2.2V
Address Command Rate:		2T
Address Drive Strength:		1.0x
Chip Select Drive Strength:		1.0x
Clock Drive Strength:		1.0x
Data Drive Strength:		1.0x
DQS Drive Strength:		1.0x
Address Fine Delay:		No delay
Address Setup Time:		1 MEMCLK
Chip Select Fine Delay:		1 MEMCLK
Chip Select Setup Time:		1 MEMCLK

Profile 1 valid
Voltage Level:			2.2V
Address Command Rate:		2T
Address Drive Strength:		1.0x
Chip Select Drive Strength:		1.0x
Clock Drive Strength:		1.0x
Data Drive Strength:		1.0x
DQS Drive Strength:		1.0x
Address Fine Delay:		No delay
Address Setup Time:		1 MEMCLK
Chip Select Fine Delay:		1 MEMCLK
Chip Select Setup Time:		1 MEMCLK

Can someone help me translate those ns values into the correct values that the bios takes in? As you can see, nvidia control panel gives me SPD values in ns whereas I need it in clocks (or whatever form the tCL-tRCD-tRP-tRAS) format is.

 

[BillParrish]

1 ns = 10 to the negative 9 seconds = .0000000001

frequency = events/time unit (something, cycles, pulses, whatever, divided by one time unit.)

Cycles per one second = frequency as used in this case, and we will use "f" as the symbol

if you take the inverse you get the fraction of a second for one event to happen.

so time = 1/f (one[second] divided by f)

at 100MHz (100,000,000 cycles per one second) taking the inverse gives: 1second/100,000,000cycles = .00000001 (7 zeros) = 10ns per cycle

1GHz: 1/1,000,000,000 = .000000001 (8 zeros) = 1ns per cycle

400MHz: 1/400,000.000 = ,0000000025 (8 zeros) = 2.5 ns per cycle

at a particular frequency, say 400MHz for example, one clock cycle/pulse takes 2.5ns and lets call that a "tick" .

In your case lets look at this for example.
Min RAS to CAS delay (tRCD): 12.500 ns

If you were running a 400MHz base clock one tick is 2.5ns and 12.5ns is 5 ticks (2.5 x 5 = 12.5) so at 400MHz clock tRCD should not be set to less than 5.

if you were running a 500MHz base clock one tick is 2.0ns and 12.5ns would be 12.5/2 = 6.25 ticks but we cannot have a .25 ticks, so round up to 7 ticks, so at 500MHz tRCD should not be set to less than 7 (6 might work if the ram chip was "great" but the odds of getting 8 "great" chips on one stick is eh, well, not good.)

DDR2 transfers data on the rising and falling edge of a tic, but for timinging purposes a tick is one whole cycle, your 400MHz memory uses 2.5ns as a "tick" it is rated 800MHz for data transfer only. Use the base FSB to determine a "tick".

Per your speed listing. At 400MHz

CAS = 5
tRCD = 5
tRP = 5
tRAS = 18

OK so much for your actual question, problem is that those timings programmed into the SPD are plain jane JEDEC timings so the chip will boot with any computer in the world that runs DDR2. What I do not know is if that readout contains ALL the SPD data. I think not.

Use SPDtool to see everything that is in there. DO NOT fark around with this program it can reprogram your spd, just fire it up and tell it to read the values, copy them and exit, there is no risk if you behave yourself

http://reference.techpowerup.com/SPDTool

 

[CoW]8(0)]

Thanks Bill, I noticed via SPDTool that my tRC value was only 6 cycles. This seems way too low as everest says that my EPP tRC is 24. But that also doesn't make sense because isn't tRC = tRAS + tRP.

So with 4-4-4-12 timings, my tRC would be 16 cycles.

 

[BillParrish]

Thanks Bill, I noticed via SPDTool that my tRC value was only 6 cycles. This seems way too low as everest says that my EPP tRC is 24. But that also doesn't make sense because isn't tRC = tRAS + tRP.

So with 4-4-4-12 timings, my tRC would be 16 cycles.

hmm on mine:

Min Act/Auto-Rfrsh Time (tRC) 57.500 ns 57.5/2.5 = 23

hmm 24 sounds about right no idea why spdtools would report that, hmm wonder what spdtool says mine is. Spdtool reports my tRC as 55ns. (22 ticks) which makes sense so now I wonder about your very low setting,

my tRAS + tRP is 5 + 18 (according to spd) = 23 so that jives close enough.

very very weird I have heard of misprogrammed ram from the factory, I would query over in the memory section. To be honest, I went through all this and tweaked mine a bit (mainly lowering tRFC from the motheboard/spd default of 52 down to 44ish) and this stuff made my head hurt so much I made it a point to take a few notes specific to my machine and promply tried to forget as much as I could. That does seem a very odd value. I do not know if everest is reading the speed or what the motherboad set ot the timing. Just never used everest.