TSMC recently (2022) presented on the hybrid pitch bonding that they use for the stacked cacheThe 7000 series, and especially the delay between the original and the 3D cache chips was supposed to be for them to sort out these issues but...it seems it was incomplete
https://www.semianalysis.com/p/packaging-developments-from-ectc
There is a lot to unpack there but TSMC is still having problems getting the cache stacked correctly, and the copper-based formulas' electrical resistance is too great.
When the chips aren't perfectly stacked the resistance goes up substantially, making a bad situation worse. They also know they have a hard ceiling of around 1.35 volts before the current itself causes the bond to break down.
Most of the delay was TSMC working with BESI to clean up the accuracy of the 8800 Ultra they use for the stacking process, it had too large a variance and it resulted in too large of a failure rate at the smaller N5 process node.