RTX 3xxx performance speculation

Nebell

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Well, there have been tons of rumors about RTX 3090 for quite some time now.
But, it's normally referred to as dual PCB GPUs.
And suddenly, with the latest rumors, it makes sense. Although it could be rather smart BS someone came up with.
But 3090 could be the next big GPU priced much higher but the one with much, much faster RT on the other side of the PCB.
Could explain the rather unorthodox cooler design with fans on both sides.
What if the latest rumors are correct? There's only 3080 with 11gb of ram and no Ti at all, but performance-wise is placed higher than x080 usually is (and maybe closer to x080Ti), 3070 being the actual successor to 2080 (and priced higher than 2070 on release) and 3060 taking 2070 place, also with a higher price point.
Meanwhile 3090, the monster with insane RT performance, created for the enthusiasts.
Wouldn't that be a smart way to increase prices?
 

Snowdog

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Well, there have been tons of rumors about RTX 3090 for quite some time now.
But, it's normally referred to as dual PCB GPUs.
More like we have several repeats of the original twitter rumors. The first time I see 3090 mentioned is kopite tweeting the RTX 3090 name, after the KatCorgi twitter thread that listed the GA102 4992 CUDA specs.
That tweet said: "Maybe, RTX 3090 will have 4992 CUDA Cores(GA102 - 3TPC = 39TPC). " It looks more like he was just guessing (hence "maybe") the 3090 name for KatCorgi rumor. Since that tweet, 3090 gets widespread usage.

To me, that just looks like the normal rumor circle jerk, that passes the same rumor back and forth.

And suddenly, with the latest rumors, it makes sense. Although it could be rather smart BS someone came up with.
But 3090 could be the next big GPU priced much higher but the one with much, much faster RT on the other side of the PCB.
Could explain the rather unorthodox cooler design with fans on both sides.
Not smart BS, just regular dumb BS.

The new cooler doesn't cool the back of the PCB, it's a flow through cooler that starts after the PCB ends. It cools things on the front of the PCB, and it has a smaller than normal PCB, which actually argues against extra co-processors.
 

oldmanbal

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They will set the pricing however necesary to hit every possible tier in the market. They've already expanded pricing up over the thousand dollar mark without AMD delivering a competing product, and based off the 3990 threadripper pricing, AMD isn't going to be giving away biggest navi.
 

Dayaks

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More like we have several repeats of the original twitter rumors. The first time I see 3090 mentioned is kopite tweeting the RTX 3090 name, after the KatCorgi twitter thread that listed the GA102 4992 CUDA specs.
That tweet said: "Maybe, RTX 3090 will have 4992 CUDA Cores(GA102 - 3TPC = 39TPC). " It looks more like he was just guessing (hence "maybe") the 3090 name for KatCorgi rumor. Since that tweet, 3090 gets widespread usage.

To me, that just looks like the normal rumor circle jerk, that passes the same rumor back and forth.



Not smart BS, just regular dumb BS.

The new cooler doesn't cool the back of the PCB, it's a flow through cooler that starts after the PCB ends. It cools things on the front of the PCB, and it has a smaller than normal PCB, which actually argues against extra co-processors.
I was hoping for the 3090ti/3090 to closer to the 10,000+ CUDA core count based on the HPC part's transistor count.

I'd have a nerdgasm and buy it just because....
 

IdiotInCharge

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They will set the pricing however necesary to hit every possible tier in the market. They've already expanded pricing up over the thousand dollar mark without AMD delivering a competing product, and based off the 3990 threadripper pricing, AMD isn't going to be giving away biggest navi.
The Threadrippers are very cheap, historically speaking... ;)

But yeah, AMD has the same market pressures that all corporations are beholden to. It's more like AMD is going back to the first FX release pricing. Get the lube ready! No free rides!
 
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I was hoping for the 3090ti/3090 to closer to the 10,000+ CUDA core count based on the HPC part's transistor count.

I'd have a nerdgasm and buy it just because....
7nm is a new node. Your are going to have to wait until 4000 series for that.

Just look at last gen, Pascal Titan was only 471mm2 from 601mm2 the previous gen Maxwell. It was the following refresh where we saw monster 700mm2+ dies.
 

noko

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Yes memory access latency is also very important. I suspect Ampere’s L2 cache will be significantly larger than Turing.

Here’s the image from the nvidia patent describing the coprocessor interface. The TTU aka Tree Traversal Unit aka RT core is inside the TPC next to the texture units accessing the same memory subsystem (MMU).

View attachment 253854D

https://patents.google.com/patent/US20200050451A1
Good stuff!

I have not seen anyone mention this, but the HiK looking plate (lowe profile, thin, vapor chamber) on the lower section would be used on the backside of the board, not the normal location for the GPU:

1592327212876.png


The position looks like it directly hooks up to the GPU on the other side of the board. That is if these are the actual design for the Ampere GPU boards/cooler. I hope Nvidia really stirs up the pot here, this would not only be for Real Time RT but could potentially transform the movie/TV industry CGI methods (Big, Big change), potentially making CPU RT rendering obsolete (maybe some hyperbola there). If Co-Processor boards can be used for RT as well (more for video/movie/TV production stuff) Wow!
 

Snowdog

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The position looks like it directly hooks up to the GPU on the other side of the board. That is if these are the actual design for the Ampere GPU boards/cooler. I
Nope. Look af the full assembled version and wireframe image:
https://hardforum.com/threads/video...tx-3080-pictured-now-thats-different.1997547/

The Fan closest to the I/O ports is in the normal front side location with the vapor chamber, and or heat pipe termination cooling the GPU chip. The second fan on the back, is after the PCB ends and flush with it. There is no way in can connect to the back of the PCB.

Edit: Visual aid. Green is PCB. All of the depth of the HSF is in front of the PCB, there is no depth left for cooling on the back.
PCB_HSF.jpg
 
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vegeta535

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LOL 3090 Ti, this is getting silly, maybe they created the SKU because Navi 2x is better than they thought it would be? Guess we'll find out very soon. Either way I'm pretty excited, I need to decide if I'm going to keep this 9900k or spend the cash and get the new Ryzen and hold on to the 2080 Ti a bit longer until the Ampere refresh releases..hmm...
No they just making a new more expensive tier of product. 3090ti is probably going to be a $2000 card while the 3080ti will be $1500.
 

noko

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Nope. Look af the full assembled version and wireframe image:
https://hardforum.com/threads/video...tx-3080-pictured-now-thats-different.1997547/

The Fan closest to the I/O ports is in the normal front side location with the vapor chamber, and or heat pipe termination cooling the GPU chip. The second fan on the back, is after the PCB ends and flush with it. There is no way in can connect to the back of the PCB.

Edit: Visual aid. Green is PCB. All of the depth of the HSF is in front of the PCB, there is no depth left for cooling on the back.
View attachment 254109

Not seeing it, getting old :D. Anyways your drawing is just someone's perception of configuration of components and not official as far as I can tell. Maybe this will help, still presumming the weird cooler design is for gaming Ampere:
AmpereCooler.jpg



What I am thinking is a whole section which covers the GPU, heatpipe etc. is not shown here. Do agree with you on configuration depth on backside of board for a normal board.

Then again I think you could be 100% correct in that the bottom section with the vapor champer in the box above is the section that on assembly would be fliped around on top of the GPU and the fan fits onto the raised surface, which in that case the fins do look rather shallow for a fan. In the above image, hard to tell it looks to be one piece making that less likely.

The above is most likely a mock up and not a real heat sink configuration, could be a configuration that is not going to be used.
 

Snowdog

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Not seeing it, getting old :D. Anyways your drawing is just someone's perception of configuration of components and not official as far as I can tell. Maybe this will help, still presumming the weird cooler design is for gaming Ampere:
View attachment 254129


What I am thinking is a whole section which covers the GPU, heatpipe etc. is not shown here. Do agree with you on configuration depth on backside of board for a normal board.

Then again I think you could be 100% correct in that the bottom section with the vapor champer in the box above is the section that on assembly would be fliped around on top of the GPU and the fan fits onto the raised surface, which in that case the fins do look rather shallow for a fan. In the above image, hard to tell it looks to be one piece making that less likely.

The above is most likely a mock up and not a real heat sink configuration, could be a configuration that is not going to be used.
Your image caption is nonsensical. How does a frontside fan and heatsink cool something on the other side of the card. It's obviously there to cool the GPU on the front of the board, as it always is.

Here is the assembled unit both sides, properly oriented vs the naked HSF:

HSF.jpg
 

Factum

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Yes memory access latency is also very important. I suspect Ampere’s L2 cache will be significantly larger than Turing.

Here’s the image from the nvidia patent describing the coprocessor interface. The TTU aka Tree Traversal Unit aka RT core is inside the TPC next to the texture units accessing the same memory subsystem (MMU).

View attachment 253854

https://patents.google.com/patent/US20200050451A1
Fun part is that I suspect NVIDIA's patent filings to be the "source" for the claimed "RT Co-processor".
If you look a this picture (FIG.1):
RTCore.jpg


That "Traversal Coprocessor"(138)...is the RT-Core....inside the GPU....but sprinkle that with some ignorance add some on fluffy feelings...and voila...we have a retard-rumor.
Another fun fact in reading the patents is that the NVIDIA hardware has capabilities (in regards to raytracing) that EXCEED DXR 1.1 specifications.
So RTX Turing is DXR 1.1+ compatible...I wonder how far off DXR 1.2 is? ;)
 

noko

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Your image caption is nonsensical. How does a frontside fan and heatsink cool something on the other side of the card. It's obviously there to cool the GPU on the front of the board, as it always is.

Here is the assembled unit both sides, properly oriented vs the naked HSF:

View attachment 254146
Thanks for the time and work on this, duh on my part, this sits right on top of the board and GPU. Have to agree with you not much room will be available on the backside of the board unless a backplate is sufficient cooling for a given chip.

Since a speculation thread, anyways here is a layout of a 2080 Ti board which is relatively stuffed or used:

2080TiPCB.png


Now Ampere is looking to be using a smaller board, if the above heat sink represents how these cards are cooled, above HS maybe just for the 3080, no idea. So will Nvidia be able to fit or shrink down the footprint for VRMs, Memory and everything else on that board and use DDR 6? Will Nvidia pull a big surprise as in using HBM, Interposer and maybe something else? Not saying one way or another.

Profile for Nano Vega 56:


NanoVegaBoard.jpg
 
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Snowdog

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That "Traversal Coprocessor"(138)...is the RT-Core....inside the GPU....but sprinkle that with some ignorance add some on fluffy feelings...and voila...we have a retard-rumor.
Another fun fact in reading the patents is that the NVIDIA hardware has capabilities (in regards to raytracing) that EXCEED DXR 1.1 specifications.
So RTX Turing is DXR 1.1+ compatible...I wonder how far off DXR 1.2 is? ;)
Yeah, a LOT of ignorance. Ignorance of what the patent actually says, ignorance of what the leaked cooler actually shows, and ignorance how cooling actually works.

Unfortunately, it's the situation were this kind of (willful?) ignorance, is lucrative, in that it's required to to create nonsensical click-bait.

Stopping and thinking about the actual patent content, the actual cooler leak, or how cooling actually works, would have killed this click-bait in it's tracks.

So, conveniently, none of that thinking wasn't done. The balance of ignorance vs profit motive will never be known.
 

MangoSeed

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That "Traversal Coprocessor"(138)...is the RT-Core....inside the GPU....but sprinkle that with some ignorance add some on fluffy feelings...and voila...we have a retard-rumor.
That's exactly what's happening. Wish more people weren't sheep though.

Another fun fact in reading the patents is that the NVIDIA hardware has capabilities (in regards to raytracing) that EXCEED DXR 1.1 specifications.
So RTX Turing is DXR 1.1+ compatible...I wonder how far off DXR 1.2 is? ;)
It certainly seems capable of fine grained control where every step of the traversal is managed by the shader core. But Nvidia openly advises against doing that for obvious reasons. It's too slow. Their mantra seems to be to make the RT core as independent as possible with as little intervention from the shaders as possible to maximize performance.

They touch on that in the Optix 6.0 overview.

https://developer.download.nvidia.c...resentation/s9768-new-features-in-optix-6.pdf

IMG_20200617_092432.jpg
 

c3k

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The technology seems very interesting. As will be any future implementation of it. However, this card is priced beyond what I'm willing to pay. So, to me, it's like reading about the latest Koenigsegg development.
 

noko

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Fun part is that I suspect NVIDIA's patent filings to be the "source" for the claimed "RT Co-processor".
If you look a this picture (FIG.1):
View attachment 254281

That "Traversal Coprocessor"(138)...is the RT-Core....inside the GPU....but sprinkle that with some ignorance add some on fluffy feelings...and voila...we have a retard-rumor.
Another fun fact in reading the patents is that the NVIDIA hardware has capabilities (in regards to raytracing) that EXCEED DXR 1.1 specifications.
So RTX Turing is DXR 1.1+ compatible...I wonder how far off DXR 1.2 is? ;)
These figures are just used for explanation and not necessarily represent every configuration that the patent covers. Patents, like most good patents covers as large a scope as possible:

0160]
The hardware unit that implements/executes such an operation is herein referred to as a “coprocessor,” irrespective of the degree to which it is integrated into the multiprocessor. Many embodiments below are described in relation to TTU 700 which operates as a coprocessor of the SM 132 by, among other things, accelerating the BVH traversal process for the SMs. However, it is not required that the coprocessor is a TTU, or even that the coprocessor is independent of the multiprocessor to a similar extent as the TTU 700 is independent of the SM 132. For example, although TTU 700 is substantially independent of SM 132 in that TTU 700 can detect many types of ray-BVH intersections without further communication with SM 132 after the ray and BVH information is received, the multiprocessors and coprocessors in example embodiments are not limited to any particular level of intercommunication between the multiprocessor and the coprocessor during the execution of the coprocessor operation.
The patent then covers communication using a communication bus, added memory, own scheduling of threads. . .
General Multiprocessor-Coprocessor Interface
[0235]
As described above, embodiments are not limited to a multiprocessor-coprocessor interface that corresponds to the interface between SM 132 and TTU 700. FIG. 15 shows a system 1500 including an interface between a multiprocessor 1502 which may be different type of multiprocessor than SM 132 and a coprocessor 1504 which may be a different type of coprocessor than TTU 700. Multiprocessor 1502 and coprocessor 1504 may communicate directly over a communication bus 1505, and both may have access to a shared memory 1506. The shared memory 1506, although shown as being located outside the coprocessor 1504 and multiprocessor 1502, is not limited thereto. In some embodiments, the shared memory 1506 may be located inside the coprocessor 1502, separately or integrated with a local memory 1520 of the coprocessor. In some embodiments, shared memory 1506 may be cache memory (e.g., such as L0/L1 cache of the TTU 700) or other memory to which the coprocessor has only read access.
[0236]
Multiprocessor 1502 is configured to concurrently execute a plurality of threads 1510, and may be further configured to command the coprocessor 1504 to perform one or more of coprocessor operations 1526 to accelerate the processing of one or a group of the plurality of threads 1510. As described above, in a SIMD multiprocessor a group of threads (e.g., a warp) may be scheduled to execute concurrently.
[0237]
The coprocessor 1504 may include its own scheduling 1524 that can ensure fair scheduling for work items (i.e. threads) submitted by the multiprocessor to the coprocessor. The coprocessor may also include its local memory (e.g., RAM) 1520 and registers 1522.
In other words it does not rule out a seperate external co-processor for this. Will Ampere have a separate chip for RT -> No idea. Appears the patent does allow that configuration how ever hard that would be hooking up to each SM on Ampere (patent for the most part ties the Transversal Co-Processor to the SM, meaning multiple Co-Processors or RT cores, like in Turing).

This is a conjecture/speculation thread, so off the wall stuff may appear.
 

Snowdog

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In other words it does not rule out a seperate external co-processor for this. Will Ampere have a separate chip for RT -> No idea. Appears the patent does allow that configuration how ever hard that would be hooking up to each SM on Ampere (patent for the most part ties the Transversal Co-Processor to the SM, meaning multiple Co-Processors or RT cores, like in Turing).
This is just falling back on "not impossible" as a defense for obviously fabricated clickbait.

It won't have a separate RT Chip, anymore than AMD or Intel will have separate Floating Point chip.
 

noko

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This is just falling back on "not impossible" as a defense for obviously fabricated clickbait.

It won't have a separate RT Chip.
No, the patent allows that configuration, if pursued or used is another thing. What Ampere will use is to be seen. I now pretty much agree it won't have a separate chip for RT, brought about by dicussion, research and what makes sense. You showed good reasoning on HSF making space on back of board rather limiting. If Coretek has some source, he did not mention it as far as I remember, he could just be wrong, interesting talk.

Will Ampere put VRMs on the back of board cooled by the backplate? Since VRMs don't need much cooling when well designed for the power load, considering the smaller area on top of the board.
 

MangoSeed

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In other words it does not rule out a seperate external co-processor for this.
Yes, it does rule it out. The patent and included diagrams describe an interface from an SM, including the snippet you quoted. An SM clearly can not communicate directly with an external chip. Nothing in the patent makes accommodations for off-chip communication.

If you’re familiar with nvidia patents they explicitly mention multiple chips and nvlink when applicable. There’s no mention of either in the coprocessor patent.
 

noko

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Yes, it does rule it out. The patent and included diagrams describe an interface from an SM, including the snippet you quoted. An SM clearly can not communicate directly with an external chip. Nothing in the patent makes accommodations for off-chip communication.

If you’re familiar with nvidia patents they explicitly mention multiple chips and nvlink when applicable. There’s no mention of either in the coprocessor patent.
https://patents.google.com/patent/US20200050451A1

Anyone interested can look at the patent themselves, conclude what they want from it.

The patent is not limited to what type of connection between the Co-Processor and SM, image further down shows example of a SM -> NVlink may or not be used, patent would still be valid since it covers any communication means between the SM and Transversal Co-Processor meaning it could be internal to GPU or external.

General Multiprocessor-Coprocessor Interface
[0235]
As described above, embodiments are not limited to a multiprocessor-coprocessor interface that corresponds to the interface between SM 132 and TTU 700. FIG. 15 shows a system 1500 including an interface between a multiprocessor 1502 which may be different type of multiprocessor than SM 132 and a coprocessor 1504 which may be a different type of coprocessor than TTU 700. Multiprocessor 1502 and coprocessor 1504 may communicate directly over a communication bus 1505, and both may have access to a shared memory 1506. The shared memory 1506, although shown as being located outside the coprocessor 1504 and multiprocessor 1502, is not limited thereto. In some embodiments, the shared memory 1506 may be located inside the coprocessor 1502, separately or integrated with a local memory 1520 of the coprocessor. In some embodiments, shared memory 1506 may be cache memory (e.g., such as L0/L1 cache of the TTU 700) or other memory to which the coprocessor has only read access.
[0236]
Multiprocessor 1502 is configured to concurrently execute a plurality of threads 1510, and may be further configured to command the coprocessor 1504 to perform one or more of coprocessor operations 1526 to accelerate the processing of one or a group of the plurality of threads 1510. As described above, in a SIMD multiprocessor a group of threads (e.g., a warp) may be scheduled to execute concurrently.
[0237]
The coprocessor 1504 may include its own scheduling 1524 that can ensure fair scheduling for work items (i.e. threads) submitted by the multiprocessor to the coprocessor. The coprocessor may also include its local memory (e.g., RAM) 1520 and registers 1522.



SepCoProcessor.png
The patent is clear on what represents a Microprocessor in regards to this patent, which is basically a SM:


SMexp.png
The patent covers an external Coprocessor with increase functionality potential hooked up to the SM. Using whatever communication method. This is very clear but folks can make up their own mind if even relevant or importantt to know. As if Ampere will extend RT performance by using such methods only Nvidia and a few others privy to the design know for sure. I have no idea if Ampere does or not, the patent does not exclude that sort of configuration and that would also be covered under the patent if ever used.

I would be very excited with something like this since it could handle most if not all of the BVH, decreasing memory loads and would basically be a paradign shift for RT (RealTime) raytracing.

Now I would like to know thoughts on how Nvidia will construct and place the different components, anything else new, on the shorter board.
 
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noko

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Thats true, we’re all free to dream. In your dream how does data flow directly from 60+ SMs to the NVlink interface?
Of course you are correct in the implimentation to all the different SMs would be, while rather interesting, I am not sure if practical or viable at this stage. Ring bus, star . . .
 

noko

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They never are. Patents are always as broad as the can get away with.

You just keep repeating the same empty defense of BS speculative click-bait.
No, just reponding to lack of NvLink statement means it can't be external to the GPU. The patent covers it and Nvidia may indeed extend capability as a possible means now or in the future.

I have no idea if what was presented was motivated to get more clicks or not, if you can read minds and motives -> power to you. Don't have to defend anything.
 

Astral Abyss

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They never are. Patents are always as broad as the can get away with.

You just keep repeating the same empty defense of BS speculative click-bait.
I mean, speculation is part of the thread title. If we can't speculate, not much point to the thread. Still speculation that they will choose that thermal design. I personally don't think they would put an RT processor on the back of the card. If anything it would be some type of chiplet, stacked design. Speaking of which, I certainly hope Nvidia is entertaining these chiplet style ideas, because their gpu sizes are getting out of control.
 
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Snowdog

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I mean, speculation is part of the thread title. If we can't speculate, not much point to the thread. Still speculation that they will choose that thermal design. I personally don't think they would put an RT processor on the back of the card. If anything it would be some type of chiplet, stacked design. Speaking of which, I certainly hope Nvidia is entertaining these chiplet style ideas, because their gpu sizes are getting out of control.
You are free to speculate Leprechauns will make special Gold Edition RTX Titans from what they found at the end of Rainbow.

The rest of us, are free to point out your speculation is empty nonsense.
 

noko

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You are free to speculate Leprechauns will make special Gold Edition RTX Titans from what they found at the end of Rainbow.

The rest of us, are free to point out your speculation is empty nonsense.
Your assuming already someone's speculation is already nonsense, could be a great talking point start; that you somehow by whatever Devine means know what the hardware will be? How else will you know if something is complete non-sense? Great, tell us then Ampere, changes, capabilities, how configured etc. Of course we will guess wrong, work through a speculation hopefully to something more meaningful -> entertainment to learning motives is what I believe most folks interested in this threads are. Others, like Trolls like to perturb, ridicule, make fun, cut off communication. Some are just pains in the ass being born that way, not their fault maybe, yet at times can give useful meaningful input between the noise.
 

Snowdog

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Your assuming already someone's speculation is already nonsense, could be a great talking point start; that you somehow by whatever Devine means know what the hardware will be? How else will you know if something is complete non-sense? Great, tell us then Ampere, changes, capabilities, how configured etc. Of course we will guess wrong, work through a speculation hopefully to something more meaningful -> entertainment to learning motives is what I believe most folks interested in this threads are. Others, like Trolls like to perturb, ridicule, make fun, cut off communication. Some are just pains in the ass being born that way, not their fault maybe.
It's not a case rejecting all speculation.

We have explained in detail why this particular bit of speculation is nonsense.
 

noko

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noko

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I mean, speculation is part of the thread title. If we can't speculate, not much point to the thread. Still speculation that they will choose that thermal design. I personally don't think they would put an RT processor on the back of the card. If anything it would be some type of chiplet, stacked design. Speaking of which, I certainly hope Nvidia is entertaining these chiplet style ideas, because their gpu sizes are getting out of control.
Could be based off of this tech Nvidia developed for multichip design.
https://spectrum.ieee.org/tech-talk...idia-chip-takes-deep-learning-to-the-extremes

While example uses deep learning,it is the network capability of 1TB/s
“The multichip module option has a lot of advantages not just for future scalable [deep learning] accelerators but for building version of our products that have accelerators for different functions,” explains Dally.

Key to the Nvidia multichip module’s ability to bind together the new deep learning chips is an interchip network that uses a technology called ground-referenced signaling. As its name implies, GRS uses the difference between a voltage signal on a wire and a common ground to transfer data, while avoiding many of the known pitfalls of that approach. It can transmit 25 gigabits/s using a single wire, whereas most technologies would need a pair of wires to reach that speed. Using single wires boosts how much data you can stream off of each millimeter of the edge of the chip to a whopping terabit per second. What’s more, GRS’s power consumption is a mere picojoule per bit.

“It’s a technology that we developed to basically give the option of building multichip modules on an organic substrate, as opposed to on a silicon interposer, which is much more expensive technology,” says Dally.
I just have a hard time seeing something like this ready for Ampere, it is not in A100 as far as I can tell.
 

Astral Abyss

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You are free to speculate Leprechauns will make special Gold Edition RTX Titans from what they found at the end of Rainbow.

The rest of us, are free to point out your speculation is empty nonsense.
Right, but what about a chiplet design? Move RT off the main core?
 

Snowdog

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Right, but what about a chiplet design? Move RT off the main core?
It's more likely that when a chiplet move happens. That each chiplet will contain some number of whole SM's, and SM's contain the RT cores.

ay_Aug2018_Updated090318_1536034900-compressed-010.png

But a chiplet GPU right now seems unlikely.
 

5150Joker

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Yes, unfortunately. Until then we get a monstrous core that will be a pain to cool. And expensive.
We'll probably see some form of MCM after Ampere is my guess, sometime in 2022 possibly. They really have no choice but to go MCM as the costs of these shrinking nodes is getting out of hand and people can't afford to keep paying more and more for GPU upgrades.
 

Snowdog

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Yes, unfortunately. Until then we get a monstrous core that will be a pain to cool. And expensive.
Chiplets are not a panacea, they don't make it any easier to cool. They are a little worse at nearly every technical aspect.

What they mainly do is improve yield, which drops cost, but not as much as many seem to think. while the chiplets do drop in cost, A chiplet GPU will pretty much require using an expensive silicon interposer to connect them together.
 

IdiotInCharge

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Chiplets are not a panacea, they don't make it any easier to cool.
There's an argument for spreading out the heat generation a bit; supposing everything else is lined up properly, see AMD failing at this with their first HDM implementations, cooling is perhaps both less complicated and more efficient. AMD has also shown this with the Ryzen 3000 (Zen 2) series with a large cache/uncore die and up to two eight-core CPU dies in a pachage.
 
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