Well, there is no longer pure CISC chips in the x86 world. Any modern x86 core is a hybrid with a CISC front-end and a RISC engine. x86 instructions are translated into uops, which are stored (uop cache), renamed, reordered, issued, executed, and retired.
Also x86 is in clear decline
RISC finally won!
The "CISC baggage" matters for larger chips as well. It is the reason why Intel and AMD have included a uop cache in Sandy and Zen.More or less. x86 does have one inescapable bit of CISC baggage. Its external instruction set is a complicated mess, and decoding it into uOps is much harder than arm/riscv/etc. For larger/higher powered chips this hasn't mattered for close to 20 years. But it's a real drag for small/low power designs; having hurt early atom on the laptop and being an important factor in Intel's mobile aspirations failing a few years back. If the future of servers becomes chips hundreds of sub-watt cores; it may again become a problem for both Intel and AMD.
The x86 tax has two parts: a fixed and a variable. The fixed part affects more to small cores. The x86 tax not only affected Intel mobile desings, it is also part of the fiasco behing Larrabe/Phi or stuff as Quark.