Relaxing memory timings for higher OCs

[vjcsmoke]

I've noticed that when some people are pushing massive overclocks, they have to relax their memory timings to achieve those speeds. How does this process work and how do I decided what timings to change to accomodate higher OCs?

IE right now my memory runs at 7-7-7-20. If I wanted to go up 200mhz, would it help to change the timings to 8-8-8-24 or something of that nature?

 

[cyclone3d]

If you are not planning on actually overclocking the RAM, you should not have to loosen the timings.

The rig in my sig is running tighter timings then stock and I am running a 200bclk fine.

You may have to up the QPI voltage and possibly the RAM voltage a tiny bit, but unless you are set on keeping those voltages lower, it really is a non issue.

 

[BillParrish]

how do I decided what timings to change to

the safest bet is to use the next "highest/loosest" JDEC standard set of timings or prevalent industry settings for the next highest CAS number (first timing number) as there is some inter-relation between the timing numbers. And yes it appears after just a quick check that 8 8 8 24 is a standard CL8 set of numbers and would be a good choice. It is interesting that CL9 seems to use 9 9 9 24 with the same 24 clock tic tRAS .

As mentioned in the post above it seems to be not nearly needed on the i series- apparently the memory multiplier on iX boards give a lot more flexibility/wider range than the older FSB systems and it seems (maybe people are just buying faster memory? /shrug) that the old problem of a minimum memory multiplier of 2.0 x FSB and low speed memory limiting the CPU overclock just does not come up.