That is assuming AMD sits on their ass for another year and half. Which is absolutely not happening given how they have been executing since zen launch. There is a reason the ice lake chips are limited to 4 core, because intel is having one heck of a time stuffing more cores there and no one is expecting any desktop HPC chips until late 2020 earliest.
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Intel shows off its chip packaging powers
- Thread starter GoodBoy
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That is assuming AMD sits on their ass for another year and half. Which is absolutely not happening given how they have been executing since zen launch. There is a reason the ice lake chips are limited to 4 core, because intel is having one heck of a time stuffing more cores there and no one is expecting any desktop HPC chips until late 2020 earliest.
Not sure how up to date you are with news related to intel 10nm desktop chips, but clearly you are wrong here. If 10nm chips were such a piece of cake to make more then 4 cores they would have done it already. The whole world knows their 10nm problems. There is a reason you don't have high end desktop chips on 10nm yet. Becuase its not a piece of cake.
IdiotInCharge
NVIDIA SHILL
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AMD can't be expected to move the bar much- they've wrung about all they can out of Zen, so aside from more cores and slightly higher clocking SKUs from binning, they're going to need a core refresh or a new node.
Whereas Intel has both.
Can't really comment on the timeline, but it looks like Intel focused on mobile first with 10nm because they've been fighting the process for years- and there's no reason to shove more than four cores into the 15w - 25w space today. Note that AMD hasn't bothered to compete in this space, despite being 'ahead', and aside from the server space, mobile is where the volume is at.
10nm means they can put more cores on the die. They're already up to what, 28 on a single 14nm die? So 40 cores might not be a stretch on 10nm.
I'm not contesting that Intel flubbed their 10nm node- but they do have products coming, and they're still competitive at 14nm with AMDs (TSMCs) "7nm". Intel clearly has more room to improve in the near future.
AMD and TSMC will continue to make improvements to the process. The first try is usually a leearning experience. Look how many tries it took Intel on 14+++ to get to the point they are at. I have no doubts AMD will make gains, most likely slow and steady like Intel has been doing for years. A few mins here, a slight uptick in IPC there, etc. Not sure how quickly Intel can respond, but so far they have been competing well with their 14nm process, just not sure how much longer that can be the case.
Quick note:. By competing I meant staying ahead, which is a toss up at this point.
Quick note:. By competing I meant staying ahead, which is a toss up at this point.
I get it but I am not expecting crazy clocks from intel either on 10nm. We will see. I think the delay in desktop processor shows struggle is real there.
also not expecting AMD to take foot off throttle. Zen 4 will be another major haul, heck zen 3 is not suppose to be small revision either. So they know what’s coming and doesn’t seem they are getting complacent. I expect AMD to keep the foot on gas.
IdiotInCharge
NVIDIA SHILL
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Intel's 'delay' is around three years- so yes, the struggle is very real.
I haven't seen anything that shows AMD has something else. As above, they do need to, as they're still really playing catch-up to Intel from a technology perspective despite being a node or two ahead.
And it needs to be said that their reliance on TSMC is a vulnerability- I do hope AMD starts sourcing from Samsung too, at the very least. They're going to need to be able to respond to contingencies and market pressures.
I think Intel's reliance on themselves was a vulnerability... If TSMC stops delivering AMD has options. Not sure how I feel about AMD spinning off their fab. On one hand it gives them multiple sources, but does put their future in others hands. I agree about playing catch up as well, 7nm is just now as fast (performance,as not clocks) as Intel's 14++ (which from what I gather you can't really directly to compare based on size alone anyways).
Not sure what your expecting to see from AMD about having something else, I'm sure they working on things. Heck they've been on a pretty consistent schedule lately. I'm sure they'll release a refresh next year, hopefully a few mhz and a couple % IPC... Maybe figure out a way to get their memory timing more consistent (as in timing to/from memory,/CPU not just bios settings).
westrock2000
[H]F Junkie
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Putting black plastic packaging on silicone...psshhh, that's so antique. That's just wasted height!
Intel Likely to Respond to Tesla Based on EMIB
Tesla is reportedly planning to use Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology for Dojo 3. EMIB is Intel's proprietary 2.5D packaging technology. 2.5D packaging refers to a method of connecting each chip by inserting a thin film called a 'silicon interposer' between the chip and the substrate.
Instead of placing a large interposer underneath the chips like conventional 2.5D packaging, EMIB connects chips with a small silicon bridge inserted inside the substrate. By placing bridges only where chip-to-chip connections are needed, chips can be arranged more flexibly and efficiently. Unlike 2.5D packaging, which is limited in die size expansion depending on the size of the interposer, it is also advantageous for composing dies over a wider area.
However, even with commercially available technology, EMIB is evaluated as being difficult to manufacture ultra-large chips at the wafer level. For this reason, the industry believes that Intel may be considering new EMIB technology and facility investments for Dojo 3.
https://x.com/Jukanlosreve/status/1953355323278070263
Tesla is reportedly planning to use Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology for Dojo 3. EMIB is Intel's proprietary 2.5D packaging technology. 2.5D packaging refers to a method of connecting each chip by inserting a thin film called a 'silicon interposer' between the chip and the substrate.
Instead of placing a large interposer underneath the chips like conventional 2.5D packaging, EMIB connects chips with a small silicon bridge inserted inside the substrate. By placing bridges only where chip-to-chip connections are needed, chips can be arranged more flexibly and efficiently. Unlike 2.5D packaging, which is limited in die size expansion depending on the size of the interposer, it is also advantageous for composing dies over a wider area.
However, even with commercially available technology, EMIB is evaluated as being difficult to manufacture ultra-large chips at the wafer level. For this reason, the industry believes that Intel may be considering new EMIB technology and facility investments for Dojo 3.
https://x.com/Jukanlosreve/status/1953355323278070263