Intel 3D Packaging Tech Gains Omnidirectionality: Big Strides Made

[erek]

Interesting? what's your opinion on this? I keep wondering about the security issues and not packaging shortfalls.

"One of the interesting features of ODI is that all the various options may be mixed and matched as desired and where it makes sense. For example it’s possible to make the base die much larger to encompass multiple top dies in a Type 2 configuration but have the edge dies be in a Type 1 configuration, allowing their power delivery to escape through copper pillars instead.



Intel has been rolling out an impressive number of new packaging technologies covering an array of capabilities and functionalities. It has taken a number of years since their first disclosure of EMIB until production of chips such as Kaby Lake G started rolling out of the line. Given Intel’s initial disclosure of ODI in late 2019, we probably won’t see this technology for another number of years – likely in the 2022/23 timeframe, however as EMIB and Foveros technologies mature, it’s likely that we will see further integration of new capabilities, beyond ODI, accelerating into production at a faster pace.



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https://fuse.wikichip.org/news/3508...l-3d-packaging-tech-gains-omnidirectionality/

 

[EniGmA1987]

Im really excited for this tech. Right now half the die space of CPUs is used by cache, and with this tech there can now be CPU dies without any cache at all, so we can basically double the core counts (power limits aside) and then stack twice as much cache as before on top or underneath the main CPU die. This not only brings more cache capability but also faster cache, as you can locate it directly on a core, instead of having to traverse a die to get to the cache.
Or in the case of an IO die and ciplets, imagine getting twice the PCI-E lanes because L3 cache can now be stacked on top of the IO die instead of taking up all the space?

This is useful in GPUs too. Nvidia brought a ton more cache space with Turing, and Ampere raises the cache even more. Imagine how many more shader cores we could get if all that cache was in its own stacked die now?

 

[DanNeely]

Im really excited for this tech. Right now half the die space of CPUs is used by cache, and with this tech there can now be CPU dies without any cache at all, so we can basically double the core counts (power limits aside) and then stack twice as much cache as before on top or underneath the main CPU die. This not only brings more cache capability but also faster cache, as you can locate it directly on a core, instead of having to traverse a die to get to the cache.
Or in the case of an IO die and ciplets, imagine getting twice the PCI-E lanes because L3 cache can now be stacked on top of the IO die instead of taking up all the space?

This is useful in GPUs too. Nvidia brought a ton more cache space with Turing, and Ampere raises the cache even more. Imagine how many more shader cores we could get if all that cache was in its own stacked die now?

for thermal reasons (the cores are hot and need as direct a connection to the heatsink as possible) I think you'd need to put the cache on the bottom of the stack. But that complicates routing since all the CPU/GPU io either needs to be placed on the edges and go around the cache; or pass through the cache chips treating part of them as an interposer.

 

[jeremyshaw]

for thermal reasons (the cores are hot and need as direct a connection to the heatsink as possible) I think you'd need to put the cache on the bottom of the stack. But that complicates routing since all the CPU/GPU io either needs to be placed on the edges and go around the cache; or pass through the cache chips treating part of them as an interposer.

That's the point of this tech update. It doesn't have to be a fully aligned "stack." Stuff can go "hanging off the edges" while other parts are "buried underneath" and combinations of existing 2.5D stacking, alleviating all of those concerns, while allowing relevant parts to have access to direct die cooling.

With any amount of luck and foresight, it would enable the less scalable bits to move off die with less penalty than existing implementations that rely on off-die interconnect methods (AMD's I/O die, Intel's hoary old Clarksdale, or IBM's buffered I/O (Centaur)). It may even improve fanout and escape routing, an increasing concern for high speed I/O.