India Develops Processor Based on Open Source RISC-V Design

cageymaru

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The Shakti Processor Project is an open source RISC-V processor developed by students in India with assistance from Intel and its 22nm FinFET Technology. The processors are based on the RISC-V ISA from UC Berkley. The current processor clocks at around 400MHz, but this a great sign of things to come from this low power ARM design. The current page is down but here is a Google cache of the specifications page.

RISC based (ARM) chips tend to be used in small, low power devices such as smart phones due to their low power usage, low footprint and relatively low cost - hence their use in the Raspberry Pi. Shakrti processor is a low-power prototype, they were interested in optimising power and area. Currently, it's clocking at 400MHz, DMIPS/MHz - 1.67.
 
" The current processor clocks at around 400MHz, but this a great sign of things to come from this low power ARM design."

There be a typo there as the design referenced in that sentence is RISC-V, not ARM.
 
tumblr_o0g3tqIbrU1tqzrm7o1_1280.jpg
 
I was reading this and it seemed to imply this was an RISC-V design and ARM.
http://www.geekdave.in/2018/07/indias-first-risc-v-is-here-linux-boots.html

RISC based (ARM) chips tend to be used in small, low power devices such as smart phones due to their low power usage, low footprint and relatively low cost - hence their use in the Raspberry Pi.

Shakrti processor is a low-power prototype, they were interested in optimising power and area.
currently, it's clocking at 400MHz, DMIPS/MHz - 1.67.
 
RISC is a description of the overall instruction set. Originally, RISC (Reduced Instruction Set Computer) used smaller instructions that could be executed quicker, where as CISC (Complex Instruction Set Computer) like X86 used larger instructions that do more per instruction but use more clocks to execute.

RISC != ARM, but ARM==RISC. The ARM (Acorn RISC Machine/Advanced RISC Machine) ISA is owned by Arm Holdings which is owned by Softbank the same way that Intel owns the X86 arch and licenses it to AMD, etc.

POWER, PowerPC, Alpha, MIPS and SPARC arches are all also RISC instruction sets.

RISC-V isn't ARM. It's actually pretty fuckin far from it. The ARM ISA needs licenced from ARM holdings (EXPENSIVE AF), whereas RISC-V is both free as in speech and free as in beer.
 
RISC is a description of the overall instruction set. Originally, RISC (Reduced Instruction Set Computer) used smaller instructions that could be executed quicker, where as CISC (Complex Instruction Set Computer) like X86 used larger instructions that do more per instruction but use more clocks to execute.

RISC != ARM, but ARM==RISC. The ARM (Acorn RISC Machine/Advanced RISC Machine) ISA is owned by Arm Holdings which is owned by Softbank the same way that Intel owns the X86 arch and licenses it to AMD, etc.

POWER, PowerPC, Alpha, MIPS and SPARC arches are all also RISC instruction sets.

RISC-V isn't ARM. It's actually pretty fuckin far from it. The ARM ISA needs licenced from ARM holdings (EXPENSIVE AF), whereas RISC-V is both free as in speech and free as in beer.
Like I said I was just going by that article. I was wondering why it started talking about ARM when it was an open source RISC-V design that was being discussed. But since I'm not an ARM, RISC, or RISC-V expert I included it.
 
Intel has invested quite a bit into RISC-V... which seems strange perhaps on its face. However RISC-V is a good option in terms of performance to efficiency... it competes well with ARM. Intel doesn't really have its own low power play anymore so why not back RISC-V where they don't have to incure 100% of the development costs.
If nothing else Intel manages to help RISC-V score a few wins and undermines ARMS position as the defacto non x86 choice.

ARM is quite scared of RISC-V.
https://www.theregister.co.uk/2018/07/10/arm_riscv_website/

Intel is investing fairly heavily in other RISCV start ups like Si-five.
https://www.sifive.com/
https://riscv.org/2018/05/sifive-announces-investment-from-intel-capital/
 
Like I said I was just going by that article. I was wondering why it started talking about ARM when it was an open source RISC-V design that was being discussed. But since I'm not an ARM, RISC, or RISC-V expert I included it.

No worries m8. Not criticizing, just clarifying.
 
RISC is a description of the overall instruction set. Originally, RISC (Reduced Instruction Set Computer) used smaller instructions that could be executed quicker, where as CISC (Complex Instruction Set Computer) like X86 used larger instructions that do more per instruction but use more clocks to execute.

RISC != ARM, but ARM==RISC. The ARM (Acorn RISC Machine/Advanced RISC Machine) ISA is owned by Arm Holdings which is owned by Softbank the same way that Intel owns the X86 arch and licenses it to AMD, etc.

POWER, PowerPC, Alpha, MIPS and SPARC arches are all also RISC instruction sets.

RISC-V isn't ARM. It's actually pretty fuckin far from it. The ARM ISA needs licenced from ARM holdings (EXPENSIVE AF), whereas RISC-V is both free as in speech and free as in beer.

Licensing isn't the only difference. RISC-V is a more RISC and clean ISA than ARM. Moreover, RISC-V is modular and includes a 128bit version: RV128I
 
As other have pointed out the article is confounding ARM with RISC-V. Morever the claim that "RISC based (ARM) chips tend to be used in small, low power devices such as smart phones due to their low power usage, low footprint and relatively low cost" is misleading as well. RISC desings are used in some of the more expensive, powerful (and power hungry) CPUs as the Oracle 32 core server CPUs and IBM POWER series CPUs. Also we have ARM chips with TDPs on the 180W range than beat the top x86 CPUs. Next a photo of THX2 SoC compared to EPYC/Xeon

AMD-EPYC-7000-Cavium-ThunderX2-Intel-Xeon-Scalable-and-E5-V1-V4.jpg


RISC-V is also being used for high-performance chips. RISC-V is the choice as accelerator for European exascale supercomputer initiative. Also a private company is building a massive 4096-core IA chip around RISC-V.
 
Next time use the report post button folks, and don't make have to clean this thread up again.
 
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