[H] Exclusive: GDDR7 Hints

erek

erek

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Found some as yet to be covered GDDR7 Intellectual Property Previews / Hints. So an exclusive for [H]. There's apparently a draft GDDR7 JEDEC specification somewhere!

"GDDR7 Memory Model
gddr7.png
GDDR7 Memory Model provides an smart way to verify the GDDR7 component of a SOC or a ASIC. The SmartDV's GDDR7 memory model is fully compliant with draft GDDR7 JEDEC Specification and provides the following features. Better than Denali Memory Models.
GDDR7 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
GDDR7 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.""


http://www.smart-dv.com/memory/gddr7.html

https://www.chipestimate.com/log.php?from=/SmartDV/GDDR7-Memory-Model/datasheet/ip/46681&logerr=1
 
Very cool. it the draft is being worked, I would expect final spec within a a year or two.

We will have to see how much further we can take GDDR6, but we knew it would be relatively short-lived! Even if they can push the standard to 20Gbps, it's not nearly the massive journey GDDR5 made (3.6 to 9.0 Gbps).
 
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Arcygenical said:
It does in the tech journalism world, if it's true. I doubt many of us belong to JEDEC.
Click to expand...

Right. If you look in The Goggles, you'll see no other coverage. Even without a website, that's an exclusive.

You don't seem to understand just how press-free EARLY draft standards releases tend to be. erek either knows someone in the industry, or signed-up for the right Synopsys tools mailing list.

I think the reason this has gotten so little leaked press is because, for the first time ever, GDDR has a true competitor in HBM2/e. I guess people just assume the next one is coming ASAP!

I would expect to see it in a video card by 2022.
 
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GDDR standards tend to mimic vanilla DDR standard in terms of cadence. GDDR7 likely implements many changes that has occurred between DDR4 -> DDR5.

I do wonder if this requires moving to a package-on-package topology as the GDDR6 currently has a rather short trace length. While I wouldn't say it is inherently possible, but a 512 bit wide implementation does not seem feasible on GDDR6. I wonder if GDDR7 would put a similar logistical challenge for 384 bit wide arrangements.
 
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