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FSB a huge difference?

I

ICE_9

2[H]4U
Joined
Feb 28, 2005
Messages
3,459
Quick question:

How does a 2 GHz 667 FSB mobile processor stack up against a 2 GHz 1066MHz FSB desktop processor compare during folding? Both should be able to complete the calculations at the same rate right? Now add in one of those Xeon processors with a 1333 FSB and what is the difference then?
 
When overclocking, chipset timings usually loosen with a higher FSB, but I don't see the hit with folding. Stages are always faster with a higher FSB. YMMV at stock speeds.

 
I have a T7200 and a E6300... Despite the fsb advantage of the E6300, the T7200 usually manage to crunch faster framerates so I can affirm this has no effect on folding. What is more important is L2 cache, cpu speed and memory bandwidth.

 
Xilikon said:
I have a T7200 and a E6300... Despite the fsb advantage of the E6300, the T7200 usually manage to crunch faster framerates so I can affirm this has no effect on folding. What is more important is L2 cache, cpu speed and memory bandwidth.
Click to expand...

I don't think you meant to type "no effect" there. Obviously it does have an effect, just less than the other factors you listed.


 
aldamon said:
I don't think you meant to type "no effect" there. Obviously it does have an effect, just less than the other factors you listed.


Click to expand...

For me, no effect = unnoticeable difference ;) You may be right it might have a effect but I think a slower fsb might be compensated by a faster memory bus or a more efficient board design.

 
Yeah, cpu speed is much more important for lower times than a higher fsb. But it will make a small difference if the cpu speed stays constant. I doubt it makes more than 10-15secs a frame, I think RAM speed would be more critical than FSB speed. I would expect that if you had a 1333 fsb cpu with DDR2-667 and a 1066 cpu with DD2-1066 the 1066 cpu would be a little quicker because of the higher mem speeds. But that's just me thinking outloud and probably confuses you more :)
 
That brings me to my second point. I currently am running that T7200 with a single stick of 1GB of 667MHz RAM. The board denotes that it's running in single channel mode. What I don't get is why won't the board run the full memory bus without having to do dual channel? The current 667 MHz memory seems to be overkill for the current mobile processors.

Also, it's pulling 50W. It has folded so far a 2604 at 33m 09s avg and now does a 2608 at 32m and 38s avg.
 
To run dual-channel, it require 2 sticks to work. It is impossible to run dual channel with just 1 stick by design. However, the fsb may not be overkill since even with just 1 stick, it is running at full fsb ;)

 
The idea of full channel was to allow for lower speed memory to keep up with the FSB. Starting back with PC3200 DDR (400 MHz) to meet the needs of a hyperthreaded chip at 800 MHz FSB. Now, with that in mind, yes it is still necessary on the desktop processors to run dual channel memory. Why then with laptop processors? Memory is fast enough for the full speed on one channel.

I guess what I am saying is, I understand dual channel memory, I just don't see the reason for it right now with mobile processors. Would be nice if I could change the memory timings to .5/1 for this board. I hate having to populate two slots of memory when their is already enough bandwidth present. I would rather pay 10 bucks less or so for 333 MHz memory to run this processor just for cost savings.

Any linux tests that will verify the current bandwidth from my memory to the processor on this?
 
As long as the memory bus is not saturated, it will not make a noticeable difference for folding. It's the same with the FSB. The only time you need more memory or front side bus bandwidth, is when it's saturated. The only work unit I know of that could do that was the QMD core proteins. They could saturate the bus on the P4's. Current work units do not have this kind of demand on hardware.

The amount of cache with some of the SMP work units will make a difference. I take a hit with my 2 meg cache E6400 on some units because of this. C2D's with 4 meg of cache do not have the penalty that the 2 meg cache CPUs do.

Personally, I would love to see what the C2D's would do with the old QMD work units. The P4's would tear through them although the hardware requirements were really high. That was the reason for the extremely high bonus points for running them.

People say that the SMP work units have sky high bonus points for running them. I doubt the PPD with them is actually all that much higher than the old QMD's. It is somewhat higher from the quick calculations I have done, but I don't think it's blown out of proportion considering the hardware requirements for running them, the fact they are beta and the importance they have for the science. A machine that can chew through SMP work units quickly generally move the science along much faster with bigger work loads than anything previously.

Sorry for going a bit off topic. It's just something I've been wanting to mention for a while. If anyone wants to continue the SMP points discussion, please start another thread.

 
I would also disagree with SmokeRngs as well. When I experimented memory overclocking, I can notice a 1-5 mins / frame difference running at higher memory fsb and tighter timings so this can play a lot. The SMP WU can saturate the memory bus as well so don't skimp on this area as well.

 
I'm not sure if this is true for c2d cpus, but on the a64 having a higher memory speed had no effect on folding times. I did a LOT of testing on this back in the day to prove that running ram:fsb 1:1 was no different than running a divider.....thus oc'ing an a64 using a memory divider performed just as well as 1:1
 
SpoogeMonkey said:
I'm not sure if this is true for c2d cpus, but on the a64 having a higher memory speed had no effect on folding times. I did a LOT of testing on this back in the day to prove that running ram:fsb 1:1 was no different than running a divider.....thus oc'ing an a64 using a memory divider performed just as well as 1:1
Click to expand...

I always found "faster" RAM to be a waste on the A64. Think about it. The transition from Socket 754 to 939 to AM2, which did something like quadruple the memory bandwidth, never did much for AMD. An incremental bump in FSB/memory bandwidth would be even more insignificant.

APOLLO said:
Hmm... that could definitely explain the lousy times I see with my quadcore Opteron sytem and the SMP client folding the latest WUs...
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I doubt my C2D results have any relevance to you. I think the Opteron is just a slow SMP folder regardless of configuration.




 
aldamon said:
I doubt my C2D results have any relevance to you. I think the Opteron is just a slow SMP folder regardless of configuration.
Click to expand...
You're probably right. Heck, I run the slower SMP WUs on my dual socket-A Athlon system and I make the deadline. That system is running at only 2.19GHz and it is more stable with the SMP client than my quad-core Opteron. AMD didn't make a huge leap in FPU performance (which is what really matters) going from their last generation architecture to the Opteron. The big change was the on-die memory controller. The next big change arrived with the dual core chips. Both are AMD firsts in the desktop market, but it's seriously lagging behind in performance now. The situation is not yet critical, but AMD better move fast with Barcelona or it will be a footnote in the annals of computing with the aforementioned innovations remembered as two of its greatest achievements.
 
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