ECC check on Intel i3 processors

Discussion in 'Memory' started by jack-jr123, May 13, 2012.

  1. jack-jr123

    jack-jr123 n00b

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    Hi all,

    It's really unclear wether the lower-end i3 processors do support (and actually use!) ECC memory when used on server motherboards with C202/204/206 chipsets.

    Intel doesn't tell anything on their product page (http://ark.intel.com/products/53422/).
    I already found this thread about this problem, but the answer is still unclear.

    With the help of jvsfms's post, I wrote this small C program that should indicate if ecc is working or not.

    I do not own an i3 processor to do the test.
    So I'm asking if someone could run this program for me?

    It can be compiled with:
    Code:
    gcc ecc_check.c -o ecc_check
    and must be run as root.

    It outputs something like this:
    Code:
    5004-5007h: 8 0 62 0
    5008-500Bh: 8 0 62 0
    The interesting part is the first byte (from the right).
    In my case the 0 means obviously that ECC is not enabled, and this is normal since I ran it on a i5 2500k.

    According to Intel's datasheet:
    0: ECC disabled
    1: ECC is active in I/O; ECC logic is not active In this case.
    2: ECC is disabled in I/O, but ECC logic is enabled.
    3: ECC active in both I/O and ECC logic
     
  2. drescherjm

    drescherjm [H]ardForum Junkie

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    I can check this on an lga1155 xeon on a C202 board if I get time tomorrow. I belive on this board memtest86 reported no ECC support but linux did report ECC using one of the tools that look at system info. I do not have a free i3 and I can not take the server offline to test this even if I did.
     
  3. meatincereal

    meatincereal [H]Lite

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    Should this work inside a VM (under ESXi)?
     
  4. mavalpha

    mavalpha [H]ardForum Junkie

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    Doesn't look like it should:
    http://www.intel.com/support/processors/corei3/sb/CS-031175.htm#10
    (The page was updated for 1155 processors as well, not just 1156.)

    Edit:
    Hmm, actually looks like it will:
    http://en.wikipedia.org/wiki/Intel_Core#Core_i3
     
  5. jack-jr123

    jack-jr123 n00b

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    No, the program must be run directly on the host. And it will not work if you try to run it on the ESXi hypervisor itself, as there is no /dev/mem device.

    @mavalpha: yeah, this is why I want to check, there is a lot of controversial informations.

    But saying that i3 support ECC memory, does not mean that it can actually use the memory correction code.
     
  6. drescherjm

    drescherjm [H]ardForum Junkie

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    It could be that the board will work with ECC installed and an i3 processor although it does not enable ECC. For these boards its very unclear if the ECC is even enabled on a xeon processor. Other than this program, I guess if you had a correction then this would show up in the machine check exception log and looking at that you could see that the ECC was indeed working.
     
    Last edited: May 14, 2012
  7. drescherjm

    drescherjm [H]ardForum Junkie

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    Here is the output for a xeon:

    Code:
    fileserver1 tmp # ./ecc_check
    5004-5007h: 10 0 62 3
    5008-500Bh: 10 0 62 3
    Code:
    fileserver1 tmp # uname -a
    Linux fileserver1 3.3.1-gentoo-btrfs-1 #1 SMP Thu Apr 12 15:56:05 EDT 2012 x86_64 Intel(R) Xeon(R) CPU E31230 @ 3.20GHz GenuineIntel GNU/Linux
    
    fileserver1 tmp # lspci
    00:00.0 Host bridge: Intel Corporation Xeon E3-1200 Processor Family DRAM Controller (rev 09)
    00:01.0 PCI bridge: Intel Corporation Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port (rev 09)
    00:1a.0 USB controller: Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 (rev 05)
    00:1b.0 Audio device: Intel Corporation 6 Series/C200 Series Chipset Family High Definition Audio Controller (rev 05)
    00:1c.0 PCI bridge: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 1 (rev b5)
    00:1c.4 PCI bridge: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 5 (rev b5)
    00:1c.5 PCI bridge: Intel Corporation 6 Series/C200 Series Chipset Family PCI Express Root Port 6 (rev b5)
    00:1d.0 USB controller: Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 (rev 05)
    00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev a5)
    00:1f.0 ISA bridge: Intel Corporation C202 Chipset Family LPC Controller (rev 05)
    00:1f.2 IDE interface: Intel Corporation 6 Series/C200 Series Chipset Family 4 port SATA IDE Controller (rev 05)
    00:1f.3 SMBus: Intel Corporation 6 Series/C200 Series Chipset Family SMBus Controller (rev 05)
    00:1f.5 IDE interface: Intel Corporation 6 Series/C200 Series Chipset Family 2 port SATA IDE Controller (rev 05)
    01:00.0 Serial Attached SCSI controller: LSI Logic / Symbios Logic SAS2116 PCI-Express Fusion-MPT SAS-2 [Meteor] (rev 02)
    03:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
    04:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
    05:05.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core)
    I finally have some concrete evidence that ECC is actually enabled as there has not been a single reported ECC correction yet.
     
    Last edited: May 14, 2012
  8. meatincereal

    meatincereal [H]Lite

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    Out of curiosity, which mobo do you have drescherjm?
     
  9. drescherjm

    drescherjm [H]ardForum Junkie

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    ASUS P8B-X B3 stepping.

    Remember my test point was for a Xeon E3-1230 not an i3. I am repeating that so no one misreads..
     
  10. xBabyJesus

    xBabyJesus n00b

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    Bump... did anyone ever check this on an i3?
     
  11. LeftSide

    LeftSide Limp Gawd

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    I can confirm that a g620 (cheap i3) running on a c204 chipset works with ECC ram.
     
  12. LeftSide

    LeftSide Limp Gawd

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    Well it works, and I'm running OpenIndiana. Does anyone know what code would prove that the ECC is actually working as it should? It's been completely stable for 2 months.
     
  13. LeftSide

    LeftSide Limp Gawd

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    After the compile in Open Indiana I try to run the file and it says 'Error mmapping the file: No such device or address'
     
  14. xBabyJesus

    xBabyJesus n00b

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    I haven't played with open indiana / opensolaris so this is just a guess... Can you make sure that /dev/mem is the correct mount point, and also verify that sys/mman.h file exists (maybe in /usr/include ?)
     
  15. drescherjm

    drescherjm [H]ardForum Junkie

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    I believe most server boards will log every single ECC correction in the Machine Check Exception log. However since this should be a rare event its highly unlikely that you have had a single correction yet that is unless your ram is bad..
     
  16. LeftSide

    LeftSide Limp Gawd

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    /dev/mem is there, but I don't know how to check the mount point. It should just be the default.
    mman.h is @ /usr/include/sys/mman.h

    I'm guessing checking the log file means getting into the bios? That would require hooking up a monitor. Not sure I'm that dedicated yet :D
     
  17. LeftSide

    LeftSide Limp Gawd

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    Maybe I could use a live USB linux distro, compile your code and check the ram.
     
  18. LeftSide

    LeftSide Limp Gawd

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    Ok, I put Ubuntu on a thumb drive and ran your code. Here are the results:

    ubuntu@ubuntu:~/Downloads$ sudo ./ecc_check
    5004-5007h: 10 0 63 3
    5008-500Bh: 10 0 63 3

    Hardware:
    ASUS P8B-M LGA 1155 Intel C204 Micro ATX
    Intel G620 Sandy Bridge CPU
    8GB (4x2) Kingston ValueRAM 4GB 240-Pin DDR3 SDRAM ECC DDR3 1066 (PC3 8500) KVR1066D3E7S/4G
     
  19. jack-jr123

    jack-jr123 n00b

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    Fantastic!

    We finally have a confirmation that these processors support ECC memory.
    At least the G620, but it should be the same with i3.
     
  20. arryo

    arryo n00b

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    i3-2120 with X9SCM:

    5004-5007h: 20 0 63 3
    5008-500Bh: 0 0 60 0

    When I compile gcc_check, it has this following warning:

    note: I have 1x 8G ram Super Talent ECC only
     
    Last edited: May 28, 2012
  21. EnderW

    EnderW [H]ardForum Junkie

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    Supermicro X9SAE
    Intel Xeon E3-1230V2
    4 x Crucial CT51272BD160B

    Code:
    5004-5007h: 10 10 66 3
    5008-500Bh: 10 10 66 3
    
     
  22. SkyMonkey

    SkyMonkey Gawd

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    Thanks for this thread and utility!

    Intel S1200KPR (C206 chipset)
    Intel Celeron G555
    Kingston 16GB (2 x 8GB) (KVR13E9K2/16I)

    Code:
    5004-5007h: 20 0 62 3
    5008-500Bh: 20 0 62 3
     
  23. danswartz

    danswartz 2[H]4U

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    I am thinking of building a relatively low-cost ZFS NAS/SAN (my current hypervisor also provides the ZFS storage), and having it serve up virtual disk files to the hypervisor via NFS or iSCSI (likely the former.) I do NOT want a non-ECC solution, since that obviates a major reason for using ZFS (e.g. having bit flips in memory go undetected and therefore the ZFS checksums show "OKAY"). Anyway, it will not be serving up large amounts of data (a single 1gb enet link), so I'm thinking of going the cheaper i3 route if I can. I see dual-core i3 of various speeds for $55-65 at around 2.5-2.7GHz which should be fine. Not sure yet on the motherboard, but I'd like to leverage some of the existing DDD3 ECC RAM I have (currently 32GB in 4 sticks, with one spare on the shelf.) The hypervisor does NOT need that much for the guests (currently they are using about 10GB of RAM). The hypervisor is on a SM X9SCL-F - might want to go for that again - any recommendations? Thanks!
     
  24. Aesma

    Aesma [H]ard|Gawd

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    i3s are more than 100$ new, are you thinking of Pentium/Celeron ?
     
  25. /dev/null

    /dev/null [H]ardForum Junkie

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    H61 chipset, i3-2100, FreeBSD9, MSI (MS-7680) is the motherboard.

    # ./ecc
    5004-5007h: 10 0 62 0
    5008-500Bh: 10 0 62 0

    If I grab a new motherboard & ecc ram, would it work with the i3-2100?
     
    Last edited: Feb 23, 2013
  26. danswartz

    danswartz 2[H]4U

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    I think I was thinking of the low-end i3 celerons. Anyway, I found I can't join such a CPU to a xeon E3 server in a xen pool, so I sprang for another E3/X9SCL-F :)
     
  27. Aesma

    Aesma [H]ard|Gawd

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    Do you mean that it lacks virtualization technologies ? Celeron and Pentium are called just that, not i3 celeron. i3 is above pentium, pentium is above celeron, just like i7 is above i5 is above i3.

    Robstar : yes it will work, but the choice of motherboards is limited, mainly Supermicro ones.
     
  28. danswartz

    danswartz 2[H]4U

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    I think I mixed some of the terms. I was thinking of the G5xx and G6xx processors. Anyway, it's a moot point now. No, the processors in question DO support vt-x, but xen is picky about mixing processor types, since they want to avoid situations where you can't migrate a guest from, say, a xeon e3 to a G5xx due to the latter missing some cpu flags features the code might be taking advantage of.
     
  29. houkouonchi

    houkouonchi RIP

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    X9SCL:

    admin@zeroshell: 12:47 AM :~# ./ecc_check
    5004-5007h: 8 0 61 3
    5008-500Bh: 8 0 61 3


    Although on another machine that does support ecc I get:

    root@dekabutsu: 12:46 AM :~# gcc ecc_check.c -o ecc_check
    chmod 75ecc_check.c: In function ‘main’:
    ecc_check.c:37: warning: format ‘%lx’ expects type ‘long unsigned int’, but argument 2 has type ‘int’
    ecc_check.c:43: warning: format ‘%lx’ expects type ‘long unsigned int’, but argument 2 has type ‘int’
    root@dekabutsu: 12:47 AM :~# chmod 755 ecc_check
    root@dekabutsu: 12:47 AM :~# ./ecc_check
    5004-5007h: ff ff ff ff
    5008-500Bh: ff ff ff ff

    Just out of curiosity is dmidecode not good enough for checking this?

    root@dekabutsu: 12:50 AM :~# dmidecode | grep -i error\ correct
    Error Correction Type: Parity
    Error Correction Type: Single-bit ECC
    Error Correction Type: Single-bit ECC
    Error Correction Type: Unknown
    Error Correction Type: Unknown
    Error Correction Type: Unknown
    Error Correction Type: Multi-bit ECC
    Error Correction Type: Multi-bit ECC

    admin@zeroshell: 12:49 AM :~# dmidecode | grep -i error\ correct
    Error Correction Type: Unknown
    Error Correction Type: Unknown
    Error Correction Type: Unknown
    Error Correction Type: Single-bit ECC

    Some random desktop machine with no ecc support:

    hptc ~ # dmidecode | grep -i error\ correct
    Error Correction Type: Parity
    Error Correction Type: Single-bit ECC
    Error Correction Type: Unknown
    Error Correcting Capabilities:
    Enabled Error Correcting Capabilities:
    Error Correction Type: None
    hptc ~ #
     
  30. /dev/null

    /dev/null [H]ardForum Junkie

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    I've tried this on my M5A99FX Pro R2.0 with 8GB ddr3-1600 ecc (single stick). Ecc is enabled in the bios:

    # ./ecc
    5004-5007h: ff ff ff ff
    5008-500Bh: ff ff ff ff

    From dmidecode:

    # dmidecode -t memory
    # dmidecode 2.11
    SMBIOS 2.7 present.

    Handle 0x0028, DMI type 16, 23 bytes
    Physical Memory Array
    Location: System Board Or Motherboard
    Use: System Memory
    Error Correction Type: Multi-bit ECC
    Maximum Capacity: 32 GB
    Error Information Handle: Not Provided
    Number Of Devices: 4

    Handle 0x002A, DMI type 17, 34 bytes
    Memory Device
    Array Handle: 0x0028
    Error Information Handle: Not Provided
    Total Width: 72 bits
    Data Width: 64 bits
    Size: 8192 MB
    Form Factor: DIMM
    Set: None
    Locator: DIMM0
    Bank Locator: BANK0
    Type: DDR3
    Type Detail: Synchronous Unbuffered (Unregistered)
    Speed: 1333 MHz
    Manufacturer: Kingston
    Serial Number: XXXXX
    Asset Tag: AssetTagNum0
    Part Number: 9965525-055.A00LF
    Rank: 2
    Configured Clock Speed: 667 MHz
     
  31. Fritingo

    Fritingo Limp Gawd

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    All CPUs from the beginning of time (well, 486s at least) will run with ECC memory installed on the motherboard. However, only memory controllers that actually support ECC memory (in Intel's case, the controller is in the CPU) will actually enable ECC functionality on that memory. If it doesn't, the memory will revert to non-ECC functionality.

    Desktop i3 (current Ivy Bridge) CPUs supporting ECC functionality here. There are three other solder-on-only i3s with support as well ("FCBGA/FCPCA"), but they are for laptop manufacturers.

    Desktop Celerons (slow, slow, slow) supporting ECC functionality here.

    Older i3 (Sandy Bridge) desktop CPUs supporting ECC functionality: none. Again, there are three solder-on laptop only ones out there, though.

    Desktop i5 & i7 CPUs (both Ivy & Sandy Bridge) supporting ECC functionality: none.

    That's it for non-Xeon desktop Intel CPUs.

    No. It would "work", but the ECC memory would be a waste of money as it would fall back to being regular memory. No desktop Sandy Bridge i3s (which is what your 2100 is) support ECC functionality, as per the Intel lists.
     
    Last edited: Mar 16, 2013
  32. Aesma

    Aesma [H]ard|Gawd

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    Does this program work with AMD CPUs or is it Intel specific ?
     
  33. EdwinE

    EdwinE n00b

    Messages:
    1
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    Apr 23, 2013
    Hardware:
    Asus P8C WS (Intel C216 Chipset)
    Core i3 3220
    Kingston KVR1333D3E9SK2/8G

    Code:
    ./ecc_check
    5004-5007h: 10 0 62 3
    5008-500Bh: 10 0 63 3
     
  34. Zolishoru

    Zolishoru [H]Lite

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    MB: Intel S1200KPR
    CPU: Pentium G2120
    RAM: Kingston KVR133D3E9SK2/16G
    Code:
    ./ecc_check
    5004-5007h: 20 0 62 3 
    5008-500Bh: 20 0 62 3 
    
     
  35. brigadeleiter

    brigadeleiter n00b

    Messages:
    1
    Joined:
    Nov 23, 2013
    MB: ASUS P9D-C/4L (C224)
    CPU: Core i3 4130
    RAM: Kingston KVR16E11/8EF

    Code:
    [SIZE="2"][B]# ./ecc_check[/B]
    5004-5007h: 20 0 63 [B]3[/B]
    5008-500Bh: 20 0 63 [B]3[/B] 
    
    [B]dmidecode -t memory[/B]
    # dmidecode 2.12
    SMBIOS 2.7 present.
    Handle 0x0050, DMI type 16, 23 bytes
    Physical Memory Array
            Location: System Board Or Motherboard
            Use: System Memory
            Error Correction Type: Single-bit ECC
            Maximum Capacity: 32 GB
            Error Information Handle: Not Provided
            Number Of Devices: 4
     
    Handle 0x0051, DMI type 17, 34 bytes
    Memory Device
            Array Handle: 0x0050
            Error Information Handle: Not Provided
            Total Width: 72 bits
            Data Width: 64 bits
            Size: 8192 MB
            Form Factor: DIMM
            Set: None
            Locator: DIMM_A2
            Bank Locator: BANK 1
            Type: DDR3
            Type Detail: Synchronous
            Speed: 1600 MHz
            Manufacturer: Kingston
            Rank: 2
            Configured Clock Speed: 1600 MHz
    
    Handle 0x0054, DMI type 17, 34 bytes
    Memory Device
            Array Handle: 0x0050
            Error Information Handle: Not Provided
            Total Width: 72 bits
            Data Width: 64 bits
            Size: 8192 MB
            Form Factor: DIMM
            Set: None
            Locator: DIMM_B2
            Bank Locator: BANK 3
            Type: DDR3
            Type Detail: Synchronous
            Speed: 1600 MHz
            Manufacturer: Kingston
            Rank: 2
            Configured Clock Speed: 1600 MHz
    
    [B]dmidecode -t processor[/B]
    Handle 0x0004, DMI type 4, 42 bytes
    Processor Information
            Socket Designation: LGA1150
            Type: Central Processor
            Family: Xeon
            Manufacturer: Intel            
            ID: C3 06 03 00 FF FB EB BF
            Signature: Type 0, Family 6, Model 60, Stepping 3
            Flags:
                    FPU (Floating-point unit on-chip)
                    VME (Virtual mode extension)
                    DE (Debugging extension)
                    PSE (Page size extension)
                    TSC (Time stamp counter)
                    MSR (Model specific registers)
                    PAE (Physical address extension)
                    MCE (Machine check exception)
                    CX8 (CMPXCHG8 instruction supported)
                    APIC (On-chip APIC hardware supported)
                    SEP (Fast system call)
                    MTRR (Memory type range registers)
                    PGE (Page global enable)
                    MCA (Machine check architecture)
                    CMOV (Conditional move instruction supported)
                    PAT (Page attribute table)
                    PSE-36 (36-bit page size extension)
                    CLFSH (CLFLUSH instruction supported)
                    DS (Debug store)
                    ACPI (ACPI supported)
                    MMX (MMX technology supported)
                    FXSR (FXSAVE and FXSTOR instructions supported)
                    SSE (Streaming SIMD extensions)
                    SSE2 (Streaming SIMD extensions 2)
                    SS (Self-snoop)
                    HTT (Multi-threading)
                    TM (Thermal monitor supported)
                    PBE (Pending break enabled)
            Version: Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz
            Voltage: 1.8 V
            External Clock: 100 MHz
            Max Speed: 3400 MHz
            Current Speed: 3400 MHz
            Status: Populated, Enabled
            Upgrade: Other
            L1 Cache Handle: 0x0005
            L2 Cache Handle: 0x0006
            L3 Cache Handle: 0x0007
            Serial Number: To Be Filled By O.E.M.
            Asset Tag: To Be Filled By O.E.M.
            Part Number: To Be Filled By O.E.M.
            Core Count: 2
            Core Enabled: 2
            Thread Count: 4
            Characteristics:
                    64-bit capable
    [/SIZE]
     
  36. uOpt

    uOpt Gawd

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    Does anybody have ECC definitely running in a non-Asus board? (also not labeled server board, that's easy)
     
  37. /dev/null

    /dev/null [H]ardForum Junkie

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    I've got it in an am2 asus board, and IIRC 2 am3/+ asus boards. The am2 I think was marketed as a "server" board (M2N-LR). I don't think the other two were, though.
     
  38. rMarkus

    rMarkus n00b

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    Hello,

    I advanced the very helpfull c-programm from jack-jr123 with decoding functions, which are based on Intel Specification.
    (Thank you jack-jr123 and jvsfms!)


    The output should now easy and not confusing to interpret.

    It looks like:
    Code:
    5004-5007h: 0 0 60 0
    5008-500Bh: 4 0 61 3
    
    Interpretation:
    ------------------
    Channel 0:
      DIMM A&B swapped: 0
      DIMM A Size:      0 MB
      DIMM B Size:      0 MB
      DIMM A dual rank: 0
      DIMM B dual rank: 0
      DIMM A DDR width: 8
      DIMM B DDR width: 8
      Rank Interleave:  1
      Enh. Interleave:  1
      ECC in IO:        0
      ECC in Logic:     0
    Channel 1:
      DIMM A&B swapped: 1
      DIMM A Size:      1024 MB
      DIMM B Size:      0 MB
      DIMM A dual rank: 0
      DIMM B dual rank: 0
      DIMM A DDR width: 8
      DIMM B DDR width: 8
      Rank Interleave:  1
      Enh. Interleave:  1
      ECC in IO:        1
      ECC in Logic:     1
    
    The first lines are the unmodified output of the original.

    Here you can download it as intel1155_ecc_check2.c.

    Compiling is the same as on the original programm and the programm must be runned as root becaus of access to /dev/mem under Linux.
    Code:
    gcc intel1155_ecc_check2.c -o intel1155_ecc_check2
    
    If ECC is fully enabled, the ECC in IO and ECC in Logic should be both 1 on populated channels.

    This will only work on Socket 1155-CPUs with two memory channels.
    On other platforms e.g. with 3 channels the registers must get another decoding and this program shows garbage, because this program not testing cpu compatibility.
     
  39. RESTfulADI

    RESTfulADI 2[H]4U

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    Feb 20, 2005
    Thanks for this oldie but goodie.

    Just ran intel1155_ecc_check2.c. on my i3-2100 and Supermicro C204 and ECC is enabled. Not sure why someone was insisting i3 sandy bridge woudn't be fully using ECC even with server chipset.
     
  40. brainsucker

    brainsucker n00b

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    1
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    Mar 31, 2016
    It seems addresses and bits are in the same place for 6-th generation i3 / Xeons.
    I think I'm going the GIGABYTE GA-X150M-PRO ECC + i3-6100 way in the near future, can any one confirm that (or similar C232/C236 + i3-6xxx) configuration works? One stupid remark on Gigabyte site worries me:
    Although that looks like some mistake according to all other sources.

    One funny thing: in current datasheets (for E3-1200 v5 datasheet vol.2 and "6th Generation Intel® Processor Datasheet for S-Platforms" vol.2) Intel is skipping description for ECC bits 12-13 of "Address decoder intra channel configuration register. (MAD)—Offset 5004h" and offset 5008h, like they don't exist, although they are clearly present on the bits diagram on the same page :)
    Hopefully they are not invalid now...