CPU waterblock testing methodologies

[BillA]

no problem Cathar,
I have precisely the same deficiency of factual data as you.
so ?
variations' magnitude, dist, all unknown

sorry, we process missing data differently
I do not posit a conclusion in advance of data, based on anticipated data - its the data that speaks
but my hypothetical question/assumption was found to be outrageous for merely assuming the opposite as you
strange

can we agree that the variation in Tim1 joints in the 775 package is not presently known to us ? (both you and I)
do you think the variation in 775 Tim1 joints could (means possibly) be low enough to get consistent temps from different cooling solutions ?
- if you do not agree with the above, then I do understand how you would be unable to support the use of IHS clad CPUs as heat sources
- but, if Tim1 were so variable then no cooling solution would be predictable
is this the case ?

why not gather some data ?
what is data ? who will do it ? then back into the public opinion court ?
jeez

 

[plywood99]

so, something that i would like clairified for myself, does anyone really know if these localized hot spots pop up anywhere in the die vs. at specific and predictable locations.

it has been previously stated that there is a temp probe located in a cool region of the proc for user feedback and a probe in a hot region of the proc for thermal protection. are there any other hot areas known?

if there are predictable locations known....it is simply too complicated/expensive to actually build a die simulator that makes the same areas extra hot, and micro probes installed in those locations?

please be kind, not like me. you guys are the pros, and i'm just trying to brainstorm.

i had an idea regarding finding hot spots if they are unknown, but it's not usefull for waterblock testing and wouldn't be easy to pull off.

Just to add to Cathar's post, there is a company currently making an ihs that supposedly carries the heat from these hot spots to cooler parts of the ihs. Very similar to tec's...

 

[Erasmus354]

This is something Cathar does quite well and should be aplauded for.

Ok first of all before I say this, please please please please please nobody take the following comment(s) the wrong way. None of them are meant in any way, shape or form to be a personal jab.

While reading this thread it came to me, another thing Cathar does very well is communication. I would wager that in technical knowledge BillA and Cathar are at least equal; BillA might be more experienced I am not sure. Cathar does a much better job of conveying his ideas. It is amazing what capitalization, punctuation, grammar and a diverse vocabulary can do to make your point more persuasive. Too often in the internet age do people get lazy with their mechanics. I do it all too often as well. There are a select few, like Cathar, who almost always are very well spoken. It really helps to make yourself much more persuasive and respected.


Sorry for the off-topic post.

 

[Cathar]

Erasmus354, thanks for the sunshine.

Bill does have more direct testing experience than I in these matters, of that there is no doubt. This is a part-time kick for me. It is a full-time career for Bill. I guess I am fortunate enough that Bill respects me enough to at least listen to my ramblings. He has sure given me hell in the past, but in return I'd like to think that I'm in a position to ask the hard questions of him too. While we're going at it hammer'n'tongs with each other, here, and elsewhere, I'd like to think that we still respect each other, even in disagreement.

Intel 775 CPU's could very well be the answer. If the TIM1 is proven to be invariable, then I will happily shut up and drop my proposed solid "mushroom IHS die-sim", because the Intel 775 solution would be a better choice, except that we still don't know Tjunction with it, and I consider that to be a critical short-coming.

So really the nub of my complaint is that we don't know Tjunction. If we knew that, then Bill could answer the questions I'm asking, it'd all be settled, and we could all move forwards.

The present situation of lack of agreement over testing really comes down to that none of the CPU manufacturers are willing to play ball, and give any testers what they need. There's no real reason not to make Tjunction available and visible, other than marketing ones.

 

[BillA]

p99
I would presume that AMD's interest in enthauast feedback is also related to the greater economic interest, and market leadership in that segment
the phase change guys have been complaining for some time of Tim1 detaching (diff coeff exp)

nooo, same as Cathar - no data to cite; but I have no conclusion already selected either

am not suggesting that Cathar is unaware, by any means; he communicates worldwide with many more than I
but this is a technical issue related to the mechanics of CPU thermal testing, and as such the 'answer' is correctly technical;
but CPU based testing has now been 'politicized' and damned w/o a single numerical value

good prejudice, crap science

nothing is invariate, why use such terms ?
can we extract useful info from the noise ?
why the fixation on a silicon temp that you have never known ?
where do you get a silicon temp today ?
someday you will understand that the IHS temp is exactly what is needed, other stuff also but that temp is key for thermal solutions; it is right in the center of everything

 

[Cathar]

good prejudice, crap science

Such a gentle lad, our Bill. A delicate flower.
I disagree (of course). Crap science comes from making assumptions.

nothing is invariate, why use such terms ?

Actually I originally just said that it varied. You said it doesn't. The opposite of variable is invariant, no?. Hence the origin of the term, and the reason for its use.

can we extract useful info from the noise ?

Noise? Are we backing away from the statements you made earlier that it does not vary?
Which is exactly what I've been asking all along. No disagreement here.

why the fixation on a silicon temp that you have never known ?
where do you get a silicon temp today ?
someday you will understand that the IHS temp is exactly what is needed, other stuff also but that temp is key for thermal solutions; it is right in the center of everything

The applicability of these three points goes straight back to the "target audience" post I made earlier. If you can't understand why people are concerned about the silicon die temp, and if you believe that the IHS temp is what is needed, then it is because you're catering to a different audience.

 

[Ice Czar]

Crap science comes from making assumptions.

errr...

slightly off topic, but all science is based on some assumptions, but you try to whittle them down to as few as possible, thus of two theories that explain the same phenomena the one with the least assumptions is the more useful

or in two words, Ockham's Razor

we are seeking a means to whittle down the assumptions that hitherto we have been forced to accept,
and more to the point on a reasonable budget

 

[Cathar]

Errr, correct. Allow me to rephrase. Crap test results can come from making assumptions.

 

[BillA]

not a debate,
I yield the field

 

[Erasmus354]

Eventhough most of this is still over my head (hopefully for not too much longer....finishing my degree can never come soon enough the more I learn) I would like to thank Cathar and BillA for sharing their thoughts and opinions here on Hardforums. I know discussions like this are usually relegated to more enthusiast places like procooling. Nevertheless I think it is nice to have a more technical discussion here every once and awhile so that the noobies can see all the work that goes on behind the scenes in both design and testing of waterblocks.

 

[R1ckCa1n]

Kiss ass


Actually good to see stimulating posts versus the normal "big bore owns ur base" type posts.

 

[Cathar]

Thing I don't understand is this. The documents linked to by Marci refer to the Tjunction, which by itself would completely satisfy me, and most any overclocker, about the temperature of the CPU/heat die. Tjunction being the temperature positionally located in the middle of the die, located between the die itself, and the CPU packaging substrate. It'd be the next best thing against the most desirable option, which would be having access to TCC readings ( TCC being the on-die thermal probe located within the ALU on P4's).

So with that, it seems that the present Intel supplied testbeds given out for validation purposes do not allow for the measurement of Tjunction. If they did, then in my mind, that would totally absolve any concerns that overclockers have, being that rather than merely knowing the IHS surface temp, we now know what's going on at the die level as well. Sure, we can argue for days about whether or not Tjunction is truly representative of the die temperature, but I can say one thing, it is better than nothing at all.

Having Tjunction, along with Tcase, would allow for at least some quantification of TIM1 in all scenarios. Intel themselves appear to clearly be using Tjunction to perform internal assessments of TIM1 as pressures vary, and since much of the call for TIM1 quantifications seem to be evidenced in geometrical and pressure variations of cooling devices, this would seem to me to be what is needed to solve the issue, and allow testers to quantify TIM1, and allow testers to quantify the die temperature in a more precise sense than merely measuring Tcase, which is itself subject to variations due to wb flatness.

Using Incoherent's flux block method to quantify TIM2, and then we have pretty much all the answers we're after.

 

[DFI Daishi]

well not to ressurect a dead thread or anything.......

i got in to talk to one of the profs who runs waterloo's microelectronics heat transfer lab, and while i don't have the strong background in heat transfer to treat this topic quantitatively......one thing that really struck me was the number of heat transfer factors depend on mounting pressure.

the way that i'm understanding it for an a64 with IHS installed......i see 4 contact resistances, 2 TIM thicknesses and internal stressing of the IHS material as being mounting pressure dependant variables that affect thermal transfer.

is mounting the waterblock multiple times really enough to control for all of that in a test bed for a64 with IHS?

how consistent is the spring mounting pressure from normal CPU retention hardware?

i know that robotech has commented that he can re-test blocks much later and get results consistent results with his heat die. i'm just wondering how close the spread is for the TTV or other test equipment that includes an IHS.

i realize that with an intel solution, the solder join isn't as compressable as the TIM 1 paste in an a64.......but i'm now pretty curious about this consistency issue.

if the tests with IHS are consistent, what procedures are needed to generate that consistency?

at this point i can see how introducing a thermocouple will change the thermal properties of the IHS and the measurements you get from the test. i don't see how that can affect two waterblocks to a different degree, when tested on the same piece of equipment.