CPU waterblock testing methodologies

[DFI Daishi]

this is just a thought, and i'm only putting it up to try and get some of the current discussion on waterblock testing into a dedicated thread.

has anyone considered how accurate a measure of a waterblock's perfirmance with a "live" CPU that uses an IHS it would be to pop off the IHS, cut a small notch in a corner of it, attach a calibrated thermal probe to an edge of the CPU die, and re-install the IHS, passing the lead for the thermal probe through the notch?

i realize that poping the IHS off and then re-installing it disrupts the factory installed TIM on the inside of the spreader, however maybe if AMD was willing to release some information on the nature of the stock TIM we could mimic the original material when re-installing the IHS.

this is so simplistic that i suspect that it has already been tried, and abandoned for one reason or another.

mainly, can this be a thread purely about waterblock testing, and can we get input from all quarters regarding thoughts as to how it should be done?

 

[Top Nurse]

Does anyone have a pic of the new Intel die simulators that Swiftech is supposedly using?

I think the only way this is ever going to come to a conclusion is if the CPU makers will start allowing for the themal temp probes that shut down the CPU to be available to us somehow. Other than that I don't see any way to test in a manner that will equate what will happen with a CPU that comes with an IHS.

Seems to me we are doing this all ass backwards. Why don't we get CPU simulators that also utilize a precision IHS so we are comparing apples to apples?

 

[DFI Daishi]

I think the only way this is ever going to come to a conclusion is if the CPU makers will start allowing for the themal temp probes that shut down the CPU to be available to us somehow. Other than that I don't see any way to test in a manner that will equate what will happen with a CPU that comes with an IHS.

i was under the impression that was exactly the diode that software temperature monitoring progs are using to detect CPU temps.

furthermore, the problem with using those diodes is that, since they were primarily intended for use in shutting the CPU down if really bad things happen, they are intended to dectect when temps get "too high" rather than detecting what the exact temperature is within the normal opperating range of the CPU.

that is why i keep saying that the software readouts are too crude to judge the performace of a waterblock by: the internal diode doesn't give a terribly accurate reading, and it was never intended to do so.

designers don't care if the CPU is actually shutting itself off at 98C, 100C, or 102C so long as it shuts itself off when it gets up near the rated limit. the calibration level of the thermal diode reflects that.

 

[Marci]

Have a read:

http://www.enerdynesolutions.com/learn_thermalinterfaces.html
http://www.intel.com/technology/itj.../art05_materialstech/p04_thermalinterface.htm
http://www.intel.com/technology/itj/2005/volume09issue04/art03_nanoandmicro/vol09_art03.pdf
http://www.apialliance.com/pdf/Archive_semiwest_05/AMD_Touzelbaev.pdf

that also utilize a precision IHS so we are comparing apples to apples?

It's not so much the precision of the iHS that's the issue. It's the TIM1 joint of Die to IHS. THe top link above states it can account for 40% of total solution thermal resistance... a variable that can be 0 to 40% is a BIG variable. Intel's IHS cannot be removed. It's Indium soldered directly to the die. Permanent solution. TIM1 repeatability must be with precision - tricky.

 

[DFI Daishi]

i was under the impression that was exactly the diode that software temperature monitoring progs are using to detect CPU temps.

furthermore, the problem with using those diodes is that, since they were primarily intended for use in shutting the CPU down if really bad things happen, they are intended to dectect when temps get "too high" rather than detecting what the exact temperature is within the normal opperating range of the CPU.

that is why i keep saying that the software readouts are too crude to judge the performace of a waterblock by: the internal diode doesn't give a terribly accurate reading, and it was never intended to do so.

designers don't care if the CPU is actually shutting itself off at 98C, 100C, or 102C so long as it shuts itself off when it gets up near the rated limit. the calibration level of the thermal diode reflects that.

you know what, never mind me. this is wrong. TN, you are correct in your above statement.

 

[plywood99]

Daishi, I seem to recall reading somewhere that the Amd tim joint is made by Shinetsu.

 

[Top Nurse]

Good Shinetsu sheet man. Must be the way they put it on that screws it up.

 

[plywood99]

Good Shinetsu sheet man. Must be the way they put it on that screws it up.

The ihs is secured with black silicone. Which I think Shinetsu makes also. I saw a silicone adhesive with good thermal properties on their site.

 

[BillA]

TN
why say "supposedly" ? if you will not give credence to the answer, skip too the question
775, groove to center for TC

"Why don't we get CPU simulators that also utilize a precision IHS so we are comparing apples to apples?"
a precision heat source ? Intel does have such, the TTV; not available to public - not worth discussing (for that reason and their confidentiality)

in testing a wb it is the temp, power, and flow that are the variables of interest; and the closer are the test conditions to those of use, the greater the confidence in the relevance of the results
and the greater the accuracy and precision with which the measurements are made, the greater the confidence that the reported value may be that described

to test a wb a heat source is required and DIYers have 2 choices; a CPU or a die sim

if a CPU, it may be 'as bought' (with IHS), or bare (only AMD)

if a die sim, 'anything' may be done in theory; but NONE on the forums have the capability to inspect a die sim face for flatness, nor to lap it flat in any case
-> for this reason the entire die sim 'debate' is something of a fraud; people are discussing a subject and glossing over the difficult/impossible parts

there is a reason so few die sims have been made, the more one understands about replicating the source, and then the actual mounting conditions, the more difficult a die sim becomes to build
- and after building and using, how does one establish a correlation between the die sim test numbers and the CPU ? (which CPU ?)
who validates the correlation ?

I am not sure who will build an exotic die sim, anyone doing so w/o considering the future is going to have a rude surprise with dual core CPUs (or a die sim with 4 hot spots, used in certain combinations ?)

whose $ are we spending ?

 

[DFI Daishi]

so, BillA, since you do not seem to be in favour of thermal die testing as such and note a lot of problems with them......

are you indicating that you do not think that they are a fair and valid tool comparing one waterblock to another, even if they are an imperfect tool for predicting waterblock performance on a real CPU?

reading all of the discussion currently going on about waterblock testing, i'm kind of wondering if we sould be drawing some distinction between the level of testing needed for doing R&D when designing new blocks and some more easily accomplished standard that could be used by independant reviewers to compare units from competing companies and verify manufacturer numbers.....just good enough to make sure that everyone is playing fair, as opposed to usefull for people professionally engineering these products.

i fully see why taking local hot spots into account in waterblock design is important, however i think reviews can still generate data usefull for comparison of waterblocks from the perspective of an aftermarket user.

Basically done by attempting to ensure that there aren't any poor heat-paths that would tend to "trap" heat, or not spread heat evenly. All waterblocks don't have a perfectly even rate of thermal dissipation at different points on the base-plate, and this unevenness also depends on what the design is doing internally. It also involves carefully balancing base-plate thickness, sometimes not merely for best possible temperatures, but to ensure that localised heat will spread quickly and evenly to the primary areas of highest convectional transfer, and ensuring that those primary convectional areas are spaced accordingly. So even if some hot spot occurs directly underneath the "worst" point-spot in terms of the block's internal geometry to deal with that localised heat load, we are balancing off the heat spreading ability of the copper vs the local primary "heat sink" locations within the block's design. As stated, this may involve choosing a base-plate thickness that does not necessarily achieve the lowest possible average die temperature across the entire die's surface (such as when purely tuning for a linear die-sim), but rather attempts to address the localised hot-spots surrounded by cool-spots that occur on real CPU's.

perhaps what i'm now saying is a bad idea, since if no one is independantly testing for performance when there are hot spots present, manufactures will totally twink their designs for putting up the best numbers on heat dies, in the interest of getting positive reviews.

 

[Top Nurse]

TN
why say "supposedly" ? if you will not give credence to the answer, skip too the question
775, groove to center for TC

"Why don't we get CPU simulators that also utilize a precision IHS so we are comparing apples to apples?"
a precision heat source ? Intel does have such, the TTV; not available to public - not worth discussing (for that reason and their confidentiality)

if a die sim, 'anything' may be done in theory; but NONE on the forums have the capability to inspect a die sim face for flatness, nor to lap it flat in any case
-> for this reason the entire die sim 'debate' is something of a fraud; people are discussing a subject and glossing over the difficult/impossible parts

I said supposedly because I don't know if they do or not, but people have posted that they do. So don't you suppose that if Intel can build a die sim that others can as well? Obviously you won't be using an Intel die sim with an AMD unit if they made if specifically to test their own product. So what makes you think that no one has the capability to inspect for flatness? I know several machine shops that have really good precision measuring tools.

 

[BillA]

DD
different tools exist with different capabilities and costs, use the most appropriate
a flat heat die may be more responsive (it should be) than a IHS clad CPU depending on the sensor and placement
but heat die sims are totally outside the maintenance capability of any user/tester that I know of

my pitch through this posturing is that as piss-poor as CPUs are as a heat source, lets attempt to define, at reasonable cost, a CPU based system that could be recommended to these 'review' sites

so far the die sim folks are stuck on the negative sell, while ignoring the problem that will plague every die owner; what does that face look like ? how do I fix it ?

TN
a user/tester (Swiftech can, as can I - but I am hardly typical)
optical flats, not mechanical
much 'old info' you should be aware of if you want to do this technobabble thing http://www.thermal-management-testing.com/

I am not aware of an AMD TTV type device; they have a completely different channel support activity than Intel, as is their device 'qualification'

 

[DFI Daishi]

DD
different tools exist with different capabilities and costs, use the most appropriate
a flat heat die may be more responsive (it should be) than a IHS clad CPU depending on the sensor and placement
but heat die sims are totally outside the maintenance capability of any user/tester that I know of

my pitch through this posturing is that as piss-poor as CPUs are as a heat source, lets attempt to define, at reasonable cost, a CPU based system that could be recommended to these 'review' sites

so, if you want testing to be confined to real CPUs for reasons of cost to the reviewer, what do you suggest?

i put up my idea, and i know that there are problems with it. you work in the industry: do you have somthing better to suggest?

so far it almost sounds like we could add a AMD heat spreader to a thermal die with a shin-etsu thermal compound in between, in order to make a heat die more like a real processor. there are certainly problems with this, but if the goal it to set things up such that the performance of competing waterblocks can be measured, while at the same time keeping the testing conditions as similar to a real CPU as possible........

i've never looked at the cost of building a die simulator, so i don't know what it would really cost. simply put: i can go out to a local machine shop and get a reasonable complicated copper part fabbed up as a one-off for less than $100 CDN, with the surface being flat to within 0.0001" of absolute. is this above what you consider a reasonable price to the reviewer, or is there is much more cost involved than getting the heat die itself made up?

 

[Ice Czar]

i've never looked at the cost of building a die simulator

$23,785

cut and paste
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Thermal Contact Resistance Measurments under Vacuum @ U of Waterloo 2003
via Stanford S.T.E.P.

Experimental Apparatus & Proceedure
All measurements were performed using the thermal interface material test apparatus at the MHTL shown in figure 1. This apparatus, as described in the publication included in the Appendix of this report uses a pair of calibrated heat flux meters with equally spaced RTD elements to measure the total heat flow rate through the joint. Heating is provided by 4 cartridge heaters in a copper block at the bottom of the test column, a liquid cooled cold plate at the top of the column acts as a heatsink for the system. Loading is perfornmed using a linear actuator connected to a lever system, and a 1000lb load cell is used to measure contact pressure at the joint. The entire measurement apparatus is contained in a vacuum chamber, and all tests are performed under vacuum conditions, p<5Pa (0.037torr). A Keithley 2700 data aquisition system is used to perform all the measurements, and data logging and control of the experiment are performed using Labview v.5.i software running on a Windows-based PC.

Two approaches are traditionally used to stabilize or eliminate heat losses, i) a guarded heater where surrounding conditions are controlled through a secondary heater and ii) a vacuum environment where conduction and convection heat losses are minimized and radiation heat losses can be controlled through a radiation heat shield.

the construction notes in the appendix are quite detailed
and relating to the actual question they used Aluminum 2024 for the flux meters

it looks like because of the tight dimensional control of the flux meters they are able to measure the temperature gradient and with the thermal conductivity of the Al 2024 determine the heat flow rate.
larger size of the flux blocks to get that gradient being the reason I assume they opted for a vacuum over the added complexity of insulation and secondary heaters when employing the RTDs
so provided the same data is available for other alloys and they are truely homogenous...

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

as BillA points out lots of variables
just look at the averaging pHastues does with his multiple mounts currently to get an idea of just one variable
any simulator is fraught with variables that seperate it from reality of an actual die
and are unique in and of themselves, useful for some quantifiable data that will seperate one waterblock from another yes, but affordable and repeatable across review sites no

 

[Cathar]

so far the die sim folks are stuck on the negative sell, while ignoring the problem that will plague every die owner; what does that face look like ? how do I fix it ?

...and this is a different problem for CPU's with IHS's in what way?

 

[Cathar]

The whole testing thing is such a massive quandary.

As always, it depends on the market being targetted. Different priorities for different people, and this is perhaps an even larger problem than any of the issue inherent to testing. Doesn't matter how good the testing is, or how accurate it is, someone isn't going to be happy because they don't perceive that information as being useful to them, unless every single thing is being tested. Then the choice of which test to put most faith in becomes overwhelming anyway for many.

OEM's want simple, with an iron clad guarantee. They want to know "Will this device pass our internal design criteria, and at what cost?". Overclocking means nothing to them. Lowest possible temps mean very little to them. They want something that will be guaranteed to meet/exceed their base-line criteria, using the methods that they choose to determine a pass/fail, and they want it for the lowest cost. The finer details, the theory, and overclocking potential can mostly take a flying leap as far as they're concerned. OEM's also form ~90% of the market too, so what they say, goes, for any company interested in turning a profit.

The scientists/thermo-engineers want pure unadultered theory, backed up with detailed experimental analysis of convectional effects and models. Overclocking means nothing to them. The sole belief is that if the rate of convectional transfer is high enough, then all else follows. Artificial die-sims abound, because all variables must be eliminated, or when not possible, controlled and error-ranges measured.

The silence-seekers want silence, and optionally bling. Nothing wrong with that at all. So long as their rig is silent, or near silent, and it cools and also possibly overclocks better than air, then that's all that's needed. Such people are probably the most content, because they're not always seeking "more"! Something to be said for the simple life, to be sure.

The overclockers want the best overclocks. For bare-dies, this is an infinitely easier problem to solve than for IHS CPU's, although for bare-dies it is still hard. First the test setup HAS TO be solely CPU bound for overclock, meaning that there is no other sub-system that is holding back the ability to overclock the CPU further. Cooling the CPU better, and the CPU alone, will increase the overclock. Generally speaking, can pretty well predict whether or not one design is on average allowing higher overclocks than another design with bare-die CPU's. With IHS's, there's a multitude of variables, and users have often witness no rhyme or reason, from CPU to CPU, or block to block. Overclocking gains with IHS cannot be predicted at all. What to do for these guys? Provide a "trend average with a gross margin of error"? Throw hands in the air and fall in with the "silence seeker" crowd? Is this the real reason why the "silence seeker" culture crowd has been growing in momentum of late?

Also, for the overclockers, these guys belief in results can be split into two main aspects. Proof of lower temperatures, and proof of better overclock. What do we do when these two criteria clash? One block provides the same or better temperatures, but overclocks worse? It has happened. These are the people who most strongly argue for "real world" results. "Don't tell me the temperatures! Tell me if it overclocks better!", or "If you can't tell me if it overclocks better, at least tell me the temperatures on a real-world test-bed!"

Part of the overall problem I think is that there are a number of different audiences, and part of the "grief" that has been occurring in the forums of late (yeah, I've been involved too) can probably be put down to which audience an interested party mostly falls into.

No easy answers. Perhaps best to focus on audience based testing? Identify who the target audience is first, what they really want to know, and then test accordingly.

I believe that grooved IHS testing falls firmly into the OEM test audience, but makes pretences to cater to the overclocking audience, but inherently cannot as the variables are too large to provide a fixed answer, hence it just falls back into the OEM camp again, or possibly into the "silence seeker" camp. I guess that this is my fundamental reason for disagreeing with IHS bound testing, as I will openly admit to having one foot firmly in each of the scientist + overclocking camps, and IHS bound testing cannot ever satisfy the goals of either.

 

[BillA]

the search for 'best' should not be done with testing, as there is no upper limit
the specific information needed should define the method (not all needs are equal, and who pays ?)
there are all kinds of people with little knowledge of and zero experience in testing, who would presume to dictate the correct form of testing
and that the pointman for the anti-CPU crowd tests with a CPU, . . . . .

you have done the community a gross dis-service Cathar, by posing questions as facts and extrapolating those 'facts' to ridiculous extremes
that the extravagant claims will now be adjusted for reality will not change the memory these kiddies have of your oft stated position that ALL (absolute, eh ?) IHS clad CPUs have Tim1 as an uncontrolled variable - when this is not the case at all, and you know it, but said it for effect

gonna take a while to clean this one up
look at it from the trenches, 'review' sites use a CPU now, are we not clever enough to help devise some improvements for their setup ?

 

[plywood99]

ALL (absolute, eh ?) IHS clad CPUs have Tim1 as an uncontrolled variable - when this is not the case at all, and you know it,

BillA, do you have data on tim joint for Intel? I know for a fact it is a mess on A64, but I have no experience with intel socket 775...

 

[BillA]

BillA, do you have data on tim joint for Intel? I know for a fact it is a mess on A64, but I have no experience with intel socket 775...

anechodotal only
seems problems abound with the AMD joint, less 'apparent' P4 problems (lower use/reporting ?), and (possibly ?) no reported 775 package Tim1 problems
- note that when Tim1 is soldered it seems to be very permanent, which to me suggests that a joint may well also be consistent over time (my whole point)

some Tim1 C/W stuff, nothing public that I know of re low temp IHS attachment
Tim1 assessment is IMO complicated by several factors which I barely/poorly understand
feel free to correct: binning by chip mfgrs is a thermally driven selection process which results in CPUs being 'grouped' actually having different thermal/performance characteristics
and for this reason the thermal output (consider leakage) of each CPU is unique, as is its overclockability
since a "C/W" determination requires both a temp and a heat load, uncertainty from either source has the same effect
"C" can be fixed by using a TC on the IHS, the heat load is more difficult

were I to presume that ALL benches had multiple thermometers correctly caled with 0.01°C resolution and comparable for flow, 0.001gpm, then the heat could be calculated
- but this just moved the level of technology from 'review site' to high-end testing

the assessment of an actual CPU heat load is the outstanding issue, to me

 

[R1ckCa1n]

The whole testing thing is such a massive quandary.

As always, it depends on the market being targetted. Different priorities for different people, and this is perhaps an even larger problem than any of the issue inherent to testing. Doesn't matter how good the testing is, or how accurate it is, someone isn't going to be happy because they don't perceive that information as being useful to them, unless every single thing is being tested. Then the choice of which test to put most faith in becomes overwhelming anyway for many.

OEM's want simple, with an iron clad guarantee. They want to know "Will this device pass our internal design criteria, and at what cost?". Overclocking means nothing to them. Lowest possible temps mean very little to them. They want something that will be guaranteed to meet/exceed their base-line criteria, using the methods that they choose to determine a pass/fail, and they want it for the lowest cost. The finer details, the theory, and overclocking potential can mostly take a flying leap as far as they're concerned. OEM's also form ~90% of the market too, so what they say, goes, for any company interested in turning a profit.

The scientists/thermo-engineers want pure unadultered theory, backed up with detailed experimental analysis of convectional effects and models. Overclocking means nothing to them. The sole belief is that if the rate of convectional transfer is high enough, then all else follows. Artificial die-sims abound, because all variables must be eliminated, or when not possible, controlled and error-ranges measured.

The silence-seekers want silence, and optionally bling. Nothing wrong with that at all. So long as their rig is silent, or near silent, and it cools and also possibly overclocks better than air, then that's all that's needed. Such people are probably the most content, because they're not always seeking "more"! Something to be said for the simple life, to be sure.

The overclockers want the best overclocks. For bare-dies, this is an infinitely easier problem to solve than for IHS CPU's, although for bare-dies it is still hard. First the test setup HAS TO be solely CPU bound for overclock, meaning that there is no other sub-system that is holding back the ability to overclock the CPU further. Cooling the CPU better, and the CPU alone, will increase the overclock. Generally speaking, can pretty well predict whether or not one design is on average allowing higher overclocks than another design with bare-die CPU's. With IHS's, there's a multitude of variables, and users have often witness no rhyme or reason, from CPU to CPU, or block to block. Overclocking gains with IHS cannot be predicted at all. What to do for these guys? Provide a "trend average with a gross margin of error"? Throw hands in the air and fall in with the "silence seeker" crowd? Is this the real reason why the "silence seeker" culture crowd has been growing in momentum of late?

Also, for the overclockers, these guys belief in results can be split into two main aspects. Proof of lower temperatures, and proof of better overclock. What do we do when these two criteria clash? One block provides the same or better temperatures, but overclocks worse? It has happened. These are the people who most strongly argue for "real world" results. "Don't tell me the temperatures! Tell me if it overclocks better!", or "If you can't tell me if it overclocks better, at least tell me the temperatures on a real-world test-bed!"

Part of the overall problem I think is that there are a number of different audiences, and part of the "grief" that has been occurring in the forums of late (yeah, I've been involved too) can probably be put down to which audience an interested party mostly falls into.

No easy answers. Perhaps best to focus on audience based testing? Identify who the target audience is first, what they really want to know, and then test accordingly.

I believe that grooved IHS testing falls firmly into the OEM test audience, but makes pretences to cater to the overclocking audience, but inherently cannot as the variables are too large to provide a fixed answer, hence it just falls back into the OEM camp again, or possibly into the "silence seeker" camp. I guess that this is my fundamental reason for disagreeing with IHS bound testing, as I will openly admit to having one foot firmly in each of the scientist + overclocking camps, and IHS bound testing cannot ever satisfy the goals of either.

That has to be the best summary of where this community stands today. Very good post, sir.

 

[plywood99]

less 'apparent' P4 problems (lower use/reporting ?), and (possibly ?) no reported 775 package Tim1 problems
- note that when Tim1 is soldered it seems to be very permanent, which to me suggests that a joint may well also be consistent over time (my whole point)

Would love to here info on Tim1 for 775. If Intel has solved Tim1 consistency problem then a nice toasty Prescott may make for a good test bed. Not the overclockers favorite right now, but as pointed out by Robotech's data, A64 is a no go.

Still at this point in time, bare die seems more reliable and indeed more consistent. But I do understand what you are saying about die flatness. I was at Robotach's house a couple months ago having him test a block I made, ( which by the way turned in better c/w numbers than Apogee ), and noticed the surface of his die sim is starting to look a little "aged" so to speak.

 

[BillA]

"bare die seems more reliable and indeed more consistent"
I know it may seem so, but accept that I alone have experience with both
that a heat die sim has greater 'sensitivity' is unquestioned; but I do think that, with some effort on technique, a CPU source would have greater utility to the community

a question also of whose interests are being served, and (sorry) cost as well

 

[Les]

"bare die seems more reliable and indeed more consistent"
I know it may seem so, but accept that I alone have experience with both
that a heat die sim has greater 'sensitivity' is unquestioned; but I do think that, with some effort on technique, a CPU source would have greater utility to the community

a question also of whose interests are being served, and (sorry) cost as well

Coming round to the concept of using "CPU source" for all but h(eff)* evaluation.

For h(eff) evaluation,I think, a uniform-flux Die-Sim is still the "answer" but requires careful modelling of the Die-Sim.
However even the "1st answer" has still to obtained (link to stalled analysis)

Crudely modelling a "1mm diam HotSpot" in a Die(Sim or CPU) "with" and "without" IHS.
The modelling is tortuous.
The analysis of Die-Sim data,to get absolute parameters, would be be sheer Hell.
I would guess that the experimental techniques would be prohibitive.
Would also not be so bold as suggest experiments for others to perform.
The choice is of method is the doer and any consideration for my thoughts are a kindness.

* Where h(eff) is defined as The Effective Heat Transfer Coefficient acting on the bp".
At constant flow-rate and temperature, I believe this is a wb characteristic which is independent of "that which is being cooled"

 

[Cathar]

you have done the community a gross dis-service Cathar, by posing questions as facts and extrapolating those 'facts' to ridiculous extremes
that the extravagant claims will now be adjusted for reality will not change the memory these kiddies have of your oft stated position that ALL (absolute, eh ?) IHS clad CPUs have Tim1 as an uncontrolled variable - when this is not the case at all, and you know it, but said it for effect

Until someone can address the following points, I will always remaining unconvinced and a staunch opponent of "hacked" IHS testing.

1) Prove that IHS's aren't the numbing and dumbing heat shield that they are, I will continue to believe that they are an anaethema to adequate testing. Robotech's P4+IHS testing bodes VERY poorly for purposes of anyone attempting to convince the masses that IHS's don't just flatten the entire playing field, and everyone should just be heading out and buying the cheapest most basic maze block around.

2) Until someone actually measures BOTH the CPU die and the IHS grooved temp, NO ONE can confidently state that the IHS is providing a consistent CPU->IHS->WB heat transfer mechanism. I see that you have chosen to ignore my salient point, that it's not just about the CPU->IHS TIM, it is about the entire heatpath itself that the IHS is affecting.

You see, while you think that I'm causing damage, I think you're causing an equal amount of damage by turning your back on the rather obvious evidence that people "in the trenches" are seeing, and yes, seeing even on "P4's with supposedly consistent TIM1 interfaces".

Measuring an IHS surface temp gives absolutely no information to the overclocking crowd, when the overclocks are still inconsistent from block to block and cpu to cpu, and yes, this happens for P4's too.

I can't for the life of me understand why you're choosing to ignore the wealth of evidence that supports that all is not well and rosy in the IHS world. Some of the results that we've both seen with grooved IHS testing run directly contradictory to the needs of the scientific and overclocking criteria, and one could probably even argue a pretty strong case that it doesn't serve the silence-seeker crowd either.

The damage that I see being done by your line of argument is that you're calling for the entrenchment of an inherently flawed testing regime which has already been shown to be ineffectual at serving those target audiences (not OEM's) which the web community review crowd serve.

Yes, there's a problem, and we need to help the web community reviewers out. That doesn't mean that we should then recommend a flawed methodology to them on the basis that "something is better than nothing". In this case, I believe it is worse than nothing, I believe it is a step backwards.

 

[DFI Daishi]

$23,785

cut and paste
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Thermal Contact Resistance Measurments under Vacuum @ U of Waterloo 2003
via Stanford S.T.E.P.

jeez, once exams are over i should really try to look up some of these people over in mech. eng.

most of my courses this semester were right next door to their primary lab building.....be interesting to get a peek at what exactly the do in their reinforced concrete, compartmentalized test cells, with blast vents......every time i walk by i've wondered, but i never really had an excuse to go int and poke around.

 

[Les]

jeez, once exams are over i should really try to look up some of these people over in mech. eng........

I use Waterloo in all my crude modelling
Unsure whether it is same department.

 

[Ice Czar]

Measuring an IHS surface temp gives absolutely no information to the overclocking crowd, when the overclocks are still inconsistent from block to block and cpu to cpu, and yes, this happens for P4's too.

but that has been and will always be the case, because of the unknown state of pristine circuitry\electromigration in any given IC chip, the only solution being a large enough sample to derive a mean average, which with high-end chips is prohibitively expensive.

I do agree with your audience breakout but overclockers have to accept that regardless of the infrastructure they invest in, it still comes down to the luck of the draw

determining the Tim1 & Tim2 variables from the pristine state\electromigration variable however - in at least rough terms - is a laudable goal
but overclocking as a test methodology is still a lottery with a cup and a half of art form and a dash of science thrown in

maybe explaining that better to the overclocking audience is what is needed as well

 

[Cathar]

determining the Tim1 & Tim2 variables from the pristine state\electromigration variable however - in at least rough terms - is a laudable goal

Oh, I wholly agree. Let's find out what those variables are. It's what I've been saying all along. Let's NOT assume that that they invariant and use this assumption to make "forwards progress" when such has not been determined.

but overclocking as a test methodology is still a lottery with a cup and a half of art form and a dash of science thrown in

maybe explaining that better to the overclocking audience is what is needed as well

I totally agree too. This is why in the testing methodology thread that I said that it is important to primarily rely on the scientific measurement aspect, and also explained heavily the problems with relying on overclocking. See here.

 

[BillA]

Cathar
when your 'argument' is based on fanciful misrepresentations, what should I be thinking ?
is this a discussion you are intent on 'winning' ?
I am not a threat to die sim testing for those wishing to do so, have I not been offering my help for years ?

from your post:
You see, while you think that I'm causing damage, I think you're causing an equal amount of damage by turning your back on the rather obvious evidence that people "in the trenches" are seeing, and yes, seeing even on "P4's with supposedly consistent TIM1 interfaces".
whose quotes are those ?
are you suggesting those are MY words ? -> from where and when ?
Stew, I have enough respect for you to not attempt to put my words in your mouth; please show the same restraint
step up to the table, today not yesterday - present technology please

775
again
775 (do please review my posts, please stop the misrepresentation)

I really would like to know of anecdotal Tim1 'related' problems with the 775 platform
anyone ?
the CPU heat source being considered (by me only ?) is a Prescott grooved for a TC

don't sweat the CPU stuff if it is not worth anything, this is the current situation with 'review' sites so no new damage is occurring;
heat dies are presently in use by JoeC and Lee so that data is still available
nothing is being eliminated (other than probable future data from Swiftech, why proffer data for the reception they got - let the review sites do it for equally ignorant readers)

 

[Ice Czar]

determining the Tim1 & Tim2 variables from the pristine state\electromigration variable however - in at least rough terms - is a laudable goal

Oh, I wholly agree. Let's find out what those variables are. It's what I've been saying all along. Let's NOT assume that that they invariant and use this assumption to make "forwards progress" when such has not been determined.

so what we need to do is recreate several Tim1 IHS and Tim2 on a die simulator\flux block
anyone have connections at Intel and AMD? Or enough info to actually try?

then compare that to a real world processor which we assign a prstine state to based on an overclock? Without direct involvement from the chip manufacturers and access to a wafer test station that would be the best we be able to manage wouldnt it?

 

[BillA]

IFR w/o instruments ?
think on it a bit IC
some logic needs to be applied as to what is being tested, how, and to develop what information

AMD or Intel ?
AMD, with IHS ? - why ?
- silicon temp how ? ext cal possible ? validation ?
Intel, 775 only, w/o IHS not possible
- silicon temp how ? ext cal possible ? validation ?

for example:
what info is needed on Tim1 ?
- how will this info be distinguished from its effect on Tim2 ?
what info is needed on Tim2 ?
- how will this info be distinguished from its effect on Tim1 ?

Cathar has put you to a wild goose chase to prove his contention; but if so then what ?
no sample size or frequency will be sufficient to prove a negative, i.e. that there is no variation, when we all know that there is
perhaps a more relevant question: is the assumed variation in Tim1 sufficient to postulate no variation in the CPU's thermal characteristics ? (such that one offsets the other ? why would Intel piss their $ away like that ? - they are not, for solely economic reasons Tim1 must be small and have the smallest possible variation)

there is a body of knowledge linked to by Marci that outlines the development of Tim1, apparently being followed by Intel
but because Cathar has repeatedly stated, should I add over and over, that Tim1 absolutely cannot be either consistent or reliable;
someone among us is going to . . . . what ?
mount a test program to show the C/W variation in 'a' low temp silicon/cu joint ?
some kinda conceit if so

will anyone answer the question: how do we presently know the silicon temp, and what is the means of validation ?
and if such is known then measuring the IHS temp in a controlled manner will provide an accurate dT, and a comparative measure of the Tim1 C/W (W is made of smoke, hopefully the same kind of smoke)

if, on the other hand we really do not know the actual silicon temp, this discourse is for fools
it will take a clever person to convince me that a make believe die temp (from a die sim ?? lol) is more useful than a verifiable IHS temp measurement
i like hard numbers more than soft logic

 

[Cathar]

Bill, all I have ever asked for, consistently, is for someone to prove that TIM1 is consistent.

Not assume. Not say "Take my word for it".

You keep saying that you believe that it is consistent, but when directly asked for evidence, none has ever been forthcoming. This means that it is just an assumption.

No one has stepped up to the table to provide that evidence. In fact, every time I call for it, here you are trying to shout me down and dismiss it.

Why?

All I know is this. If people are going to spend effort on testing, they'd want to be damn irrefutably sure that they're not just measuring the effects of some variable.

What is so, so wrong with asking for that?

 

[Ice Czar]

they where rhetorical questions \ Gedankenexperiments
my plate is so full as to be overflowing already
I will eventually glean the best and brightest ideas from this and other threads to build a simulator,
but have direct orders that its not a priority from Kyle

 

[BillA]

Cathar, #29 and before

I really would like to know of anecdotal Tim1 'related' problems with the 775 platform
anyone ?
the CPU heat source being considered (by me only ?) is a Prescott grooved for a TC

assumptions apply equally, no ?

I am now curious, of the experience (of others) referred to by you, do you have a single instance of a 775 'problem' ?
more than one ?

it seems some 775s are ok ?? are some also bad ?
do you know or are you speculating ?

 

[Cathar]

Bill, when attempting to measure something, one does not start with an unknown variable and then assume that it is invariant. Basic procedural practise.

 

[BillA]

Bill, when attempting to measure something, one does not start with an unknown variable and then assume that it is invariant. Basic procedural practise.

cute answer, object to the form

do you have a moment to answer the question about 775 experience ?

 

[Cathar]

cute answer, object to the form

do you have a moment to answer the question about 775 experience ?

Yes, I have read of people's concerns, and have engaged in one email discussion about it. Nothing specifically concrete, not enough evidence to form a strong conclusion, could've been other factors, but certainly enough to raise the strong possibility that such variability exists. This is the exact problem though. Not enough evidence to say one way or the other. Ordinarily I would just leave it at that, until someone comes along and starts proposing that everyone starts testing using a quite possibly flawed assumption about something which has not been quantified.

Again, as far as overclockers and scientific measurements is concerned, what is also of primary importance here is the temperature of the CPU (not from the numb'n'dumb probe though). Without that, how can you be sure?

Your turn. I've asked you quite pointedly to show where it is invariable and consistent, for purposes of good procedural practise. Where is that evidence? Or shall we return to the usual fare of answering a direct question with another question again, or dismissively fobbing off concerns and avoiding answering the question altogether?

There is no hidden agenda here. It is a simple straight-forward concern. Prove that it is invariable, and I will shut up.

 

[DFI Daishi]

so, something that i would like clairified for myself, does anyone really know if these localized hot spots pop up anywhere in the die vs. at specific and predictable locations.

it has been previously stated that there is a temp probe located in a cool region of the proc for user feedback and a probe in a hot region of the proc for thermal protection. are there any other hot areas known?

if there are predictable locations known....it is simply too complicated/expensive to actually build a die simulator that makes the same areas extra hot, and micro probes installed in those locations?

please be kind, not like me. you guys are the pros, and i'm just trying to brainstorm.

i had an idea regarding finding hot spots if they are unknown, but it's not usefull for waterblock testing and wouldn't be easy to pull off.

 

[Cathar]

so, something that i would like clairified for myself, does anyone really know if these localized hot spots pop up anywhere in the die vs. at specific and predictable locations.

Yes, if you have a die functional unit map, it is fairly predictable. It does also depend on what the CPU is doing as well though. The instruction decoder, register stack, and main ALU are the consistently major hot-spots. Beyond that, it depends on what is being run, and which functional unit is getting worked hard. L1 cache can also get warm too, but primarily depends on the tightness of the loops.

it has been previously stated that there is a temp probe located in a cool region of the proc for user feedback and a probe in a hot region of the proc for thermal protection. are there any other hot areas known?

Yes, see above, but none that could be consistently used for all types of things that the CPU can possibly do.

if there are predictable locations known....it is simply too complicated/expensive to actually build a die simulator that makes the same areas extra hot, and micro probes installed in those locations?

Can be done, and has been done. Fairly expensive though I believe. Outside of the affordability of the average testing punter, just as most specialised applications tend to be.

 

[plywood99]

there is a body of knowledge linked to by Marci that outlines the development of Tim1, apparently being followed by Intel
but because Cathar has repeatedly stated, should I add over and over, that Tim1 absolutely cannot be either consistent or reliable

Billa, I read Marci's links with great interest. Conclusion I have from them is that Intel is not quite happy with current tim1, although acceptable for time being. Main problem being thermal expansion differences between silicon, tim1 and ihs. Note the date for article is November 05. So tim1's mentioned are for future products, not current 775 series. You said before that you had data for 775? How many chips did you test? Enough to make a general statement? Empirical data? I really would like to see data on 775 series, but none so far.

Also of interest was the Amd article mentioning the neccesity to include enthusiast communities feedback concerning ihs/tim. This seems to be an area you are unaware of or choose to ignore. Although feedback from community may be anecdotal, it should not be ignored. IIRC it was Fugger who advised Intel on the current 775 ihs mounting. Point is, one has to step out of the lab every now and again and listen to what community is saying. This is something Cathar does quite well and should be aplauded for.