@Corsair 4x 1GB sub timings -SPD program.

[BillParrish]

I buy and use only Corsair for my personal and client builds and I know you have nothing to do with the rest of your day if I don't ask you a really tough question. So hopefully my business/brand loyalty will buy me some consideration and coupled with your huge amounts of idle time and superior knowledge and technical resources will allow you to really investigate this and save many a user/customer from ram hell. /end shamelss suck up

And while it occurs with all manuf memory, tag, your it.

Some people have issues running 4 x 1 GB on Intel boards despite single and pairs of the memory passing memtest fine. And many more people do not have issues 4 x 1GB but they are Gods special people and do not need our help.

It occurred to me that many of the 4 x 1GB configurations people use are made up of a pair of 2 x 1GB matched sets. I see that Corsair sells a 4 x 1 GB matched set.

The only thing I can think of to cause such random issues as some people have no problem and other people have waking nightmares is that due to signal path length, buss loading, and who knows what else involved with populating 4 slots. Some sub timing or drive strength or something else we do not have access to in the typical bios settings might be marginal when using a 2 x 1GB pair in those 3rd and 4th slots.

So my question(s) is/are,

Is there any significant difference in the details of the SPD or EPP programming for the 4 x 1 GB kit that might explain/help/resolve a 2 x 1GB x 2 causing issues?

If I was a super duper memory engineer and was having issues on my personal machine and was willing to take all responsibility and void the warranty, with 4 sticks installed (that worked fine in just pairs of 2 ) what programmable parameters on the last two (or all) sticks would I want to look at with a suspicion that loosening or changing the parameter might help stability with all 4 sticks installed (even at the expense of a little speed) ?

I have read/heard that on Intel MCH's 5 5 5 15 should be the tightest "normal" timings used with 4 sticks installed. I cannot find that in the MCH data sheet, JEDEC (what I can get) etc. I think this is mainly a holdover from the baisc Intel design following JEDEC to the letter of the spec and actual real world would depend on the board and bios. Any comment ? (This is for extra credit, the above two questions are what I really need to know. )



Many thanks even though I know you will just be able to pull an enlightening answer out of the vast memory store that is your brain in 7.8uS and be a hero.
Regards:
Bill Parrish.

P.S. I completely will understand if the answer is; that information is proprietary and the solution is to buy a set of 4 matched sticks. Will not be happy but I will get over it.


"Give a man Memset and he is enlightened, give a man Spdtool and he can fark stuff up royal. " - Ivonne Vutcantboot 2006.

 

[Mike Clements]

Bill, that information is proprietary and the solution is to buy a set of 4 matched sticks. I realize you will not be happy with this answer but, you'll get over it.

Just kidding

I'll have to ask about the SPDs but, I think they are identical on any single PC8500C5D module and therefore the same on kits of TwinX or QuadX. I say on the PC8500C5D as that is the only Quad kit we offer right now.

From the personal tweaking I have done, 4,4,4,12 timings are solid on AM2+Nvidia , Intel 975 and P35, and Nvidia 680i and 650i chipsets with 4 x PC6400s. It's been a while since I did any extensive 4 up testing so I can't remember at what OCing speeds for each I had to loosen timings. I have not tested 4 up on 965s but, based on forum feedback, the 965s don't like 4 up very much at all.

If I understand the other parts of what you are asking, then I think the root of the problem is going to trace back to the NB voltages and the bus loading. In theory on a properly designed MOBO, the voltage regulation at any single DIMM slot is going to be the EXACT same over any of the 4 slots. It should not waver under load to the extent that you have to loosen timings, raise Vdimm, etc when going to 4 DIMMs.

Therefore, if the default drive strength is adequate for a single DIMM, then that same drive strength should be fine for 1,2, or 4 DIMMs if the MOBO is supplying the voltages properly. (Let's not even get into droops here) Then with 4, it's the NB that will then be taking a beating. I think the NBv and the NBvtt and then the cooling are the keys. This has been much more apparent to me on the Nvidia 590, 650I, and 680i as they run VERY hot at stock and of course hotter if you raise the appropriate voltages to compensate for 4 DIMMs.

 

[BillParrish]

Thanks Mike, aye if you would check on that spd programing when you get a chance.

Gah, back to the Intel MCH documents and a crash course on "on die termination".

 

[Mike Clements]

Bill, do you use any IM programs, AIM or MSN? I have both.