Cerebras is still at it! Enter the Dinner plate CPU (WSE-3)

[lostinseganet]

More? MOARR! How about 4,000,000,000,000 Transistors at 5nm?!

https://www.zdnet.com/article/ai-startup-cerebras-unveils-the-largest-chip-yet-for-generative-ai/

View: https://www.youtube.com/watch?v=f4Dly8I8lMY

When they get to 3~2nm they might actually have a Billion Million Transistors...

 

[ManofGod]

And so begins Skynet.

 

[pendragon1]

also, see above... can we stop marching towards terminator, please?!

 

[Zarathustra[H]]

The yields must be interesting

 

[socK]

But can it infer a video of Crysis

 

[Teenyman45]

Just think of a single bent pin...

 

[lostinseganet]

The yields must be interesting

It's near 100% because they overcompensate by building more chip than needed so that the failure rate
of the broken pieces does not affect the promised performance of the leftover fixed pieces.

 

[LukeTbk]

44 gb of on chip memory..... seeem hard to find price, even if the "article" or more so company press relese talk about it, the wse-1 was around $2 million according to this: https://wccftech.com/cerebras-unveils-7nm-wafe-scale-engine-2-largest-ai-chip-ever-built/

 

[Absalom]

Cool company. They are actively defying the whole notion of wafer attrition.

 

[LukeTbk]

https://www.anandtech.com/show/1662...ne-two-wse2-26-trillion-transistors-100-yield

Cerebras achieves 100% yield by designing a system in which any manufacturing defect can be bypassed – initially Cerebras had 1.5% extra cores to allow for defects, but we’ve since been told this was way too much as TSMC's process is so mature.

Isn't almost all chips design allow for some non-working core (and often much more than 1.5% on much smaller chips) and yet does not have perfect yield at all ?

A it would be much more than having extra core to achieve high yield, it has complete redundancy:
84 processing tiles, similar to individual chips, and each tile has redundant processor cores, memory, and I/O. When one part of a tile fails, the extra functions are substituted in their place through software tools

So balancing giant amount of waste with united giant amount of cache memory and interconnect speed and you could still have chips with not enough working unit to be pratical.

 

[KazeoHin]

"So, tell me again, how big is your chip?"

Cerebras:

 

[sleepeeg3]

How much is it? I have some tough word processing to do.