ATI 4870 X2 Will Have Shared Memory

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RavenousNewt

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I was recently looking over an artical at techPowerUp.com, when I saw a sceenshot of GPU-Z as proof of an amazing number achieved in 3D Mark Vantage. The artical was about Two 4870 X2s getting a score of X12515. GPU-Z reported the VRAM as being 1GB. I have looked at screens of 3870 X2s in GPU-Z and they say there is only 512 MB of onboard RAM.
I would say this is a good sign that not all is lost in the hope of Shared Memory on R700.:D
Oh, and here is the link: http://www.techpowerup.com/64351/Two_R700s_Churn-out_X12515_in_3DMark_Vantage.html Click on the Picture and you can just make it out!
 
mm, interesting! that means they did some serious work under the hood to be able to enable that and not waste te memory mapping the same thing to both.
 
I will wait until a reliable and official source confirms this information (memory is shared) before opening a bottle of Champagne...
 
Yes, supposedly the x2 card is a "dual gpu" solution rather than "crossfire on a stick". So the memory isnt shared as 2 sets of 512 like the 3870 and gx2 were.
 
This brings the total on-board video bandwidth to a stellar 250.8 GBps.
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That suggests the memory is not shared. Or at least, each GPU has its own memory interface, and any access to the "other half" of memory would have to go across their interconnect which will probably have way less bandwidth than 125 GBps.
 
The GDDR5 have a mode where they can be connected to two controllers at once. Each controller only get half the chip's bandwidth but you get shared memory (and being GDDR5 even half of full speed is plenty).

People, this whole shared memory thing news is at least two months old. Go read up on the GDDR5 white paper from Qimonda.
 
Xeth said:
That suggests the memory is not shared. Or at least, each GPU has its own memory interface, and any access to the "other half" of memory would have to go across their interconnect which will probably have way less bandwidth than 125 GBps.
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True but they really don't need that much bandwidth between the cores. Ideally the only data that would have to go between cores would be texture lookups, which are rather small in comparison to bandwidth consumed by AA and rendering operations.

This might also be the reason why normal crossfire setups are consuming an extremely high amount of bandwidth atm.
 
clamoe4.png
 
Hypernova said:
The GDDR5 have a mode where they can be connected to two controllers at once. Each controller only get half the chip's bandwidth but you get shared memory (and being GDDR5 even half of full speed is plenty).

People, this whole shared memory thing news is at least two months old. Go read up on the GDDR5 white paper from Qimonda.
Click to expand...

That's not true. The mode you're talking about allows two chips to be connected to a single controller. Not two controllers to a single chip. All it does is allow you to double memory capacity while halving the bandwidth available from each chip. So same bandwidth and double memory capacity. Once the higher density GDDR5 chips come out 2GB cards may be possible but seems a bit excessive.
 
Dude, this Shared Memory thing isn't over yet, at least not until the NDA is lifted. So the fact that GDDR5 can be hooked up in that manner only confirms that the Memory will be Shared. It just won't need a new Controller to do so.
 
Anarchist4000 said:
That's not true. The mode you're talking about allows two chips to be connected to a single controller. Not two controllers to a single chip. All it does is allow you to double memory capacity while halving the bandwidth available from each chip. So same bandwidth and double memory capacity. Once the higher density GDDR5 chips come out 2GB cards may be possible but seems a bit excessive.
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Touché, although splitting a controller in half you can probably use the one half for communication. Not sure if this is possible but that would mean that each GDDR5 chip will have concurrency as only one controller has read/write access. The other GPU only access the MC of the other GPU and not actually the memory itself.
 
Here's what I mean:
clamak3.png


For GPU B it feels just like addressing local RAM since the controller handles the jump. There will be a hit on latency but I don't know how much.
 
In that scenario you would end up with half the bandwidth. I already looked at the pinouts for the GDDR5, if you're in clamshell the other pins are simply disabled. Only one controller can be connected to a chip at a time. If you cut the link in half and run the other half to the other core then you'd be sorely lacking for bandwidth. It'd be like running two 4870's with the same bandwidth as a single unless you significantly increased the speed of the memory.

They'd be much better off with some form of high speed connection between the two memory controllers. I'd guess 20GB/s in each direction would be more then enough. Keep in mind the caching seems to be really efficient with the 4x00 series as well. Hence some of the crossfire benchmarks showing >100% increases in framerate.
 
Anarchist4000 said:
In that scenario you would end up with half the bandwidth. I already looked at the pinouts for the GDDR5, if you're in clamshell the other pins are simply disabled. Only one controller can be connected to a chip at a time.
Click to expand...

One ram chip per controller yes, but I'm proposing that you have the controller from the two GPUs talk to each other using the spare link in clam shell mode. Now whether the MC can accept memory fetch from that interface I have no idea.
 
if it isn't a shared memory then it would be just a new 3870 card. I am hoping that they pulled it off because I am waiting on this card/
 
Don't laugh when I say this, but I get a good portion of my info from Fudzilla.com . Most of the editors are Clueless Tools, but Faud Abazovic has delivered consistantly correct info about RV770 before many others!
I first heard that RV770 would have 800 shaders way before anyone else. So don't discount the Shared Memory control idea just yet. After all, NordicHardware isn't the final authority on all things graphics.:rolleyes:
 
So now we know that because it has 16 x 512 Mib memory chips and it shows as 1024 MiB, it looks like it will have 1 gig of usable memory! Looks like we don't have to cope with the problems of afr anymore.
Andreas G isn't better than any random speculator at a forum of your choice.
 
i wonder if when the chip interconnect is enabled, that links the memory to appear as one pool?
 
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