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That isn't entirely true. First of all I remember some site doing some math and making a guess that Fermi was about 20-22 stages of pipeline in each of their cuda cores.
Just a heads up none of these products will be available until mid-late 2017, so there is still the possibility of a sort of production exclusivity (or what I think in the case of Nvidia is buying a massive chunk of the production order now-future and so tying it to them), but agree not sure if SK Hynix can be tied down as it has many collaborations although those companies inlcuding AMD probably get preferential orders.
While Altera did go into sampling status Oct 2016 I am not sure it includes the MX family (HBM2 spec version) and the expected shipping date for the MX is mid 2017 earliest.
Looking at Xilinx, the Ultrascale+ HBM (as they call it) is only on a roadmap to date and maybe late 2017, also the product has a spec of 32GB and 64GB HBM2 memory so that cannot be this release.
I double checked other sources and seems correct, also re-inforcing this the only Virtex Ultrascale+ eval board available is the DDR4.
I must say I am having problems confirming what memory Xilinx is using (well I guess they were expecting 8Hi so narrows it down, or maybe 8GB density stack fo the 32GB model *shrug*); I am trying to find a specific presentation I have/read that goes into a bit of detail from Xilinx but a nightmare to find.
Cheers
That is a good point and also 1st time I noticed the structure that uses only up to 2 HBM stacks in the largest model, various articles had it as GB rather than Gb bah.
That isn't entirely true. First of all I remember some site doing some math and making a guess that Fermi was about 20-22 stages of pipeline in each of their cuda cores.
Secondly, AMD was claiming 20% or so higher performance at the same clock with the same shader cound from Fiji/Hawaii -> Polaris.
Lastly, check this slide out, right from AMD: (Sorry It's huge)
It is still a good point you raise because the slide is deliberatley vague, all one can deduce is higher clock speeds, IPC could be down to as you say the ability of the NCU to mix packed maths.That isn't IPC
Edit if they are comparing FP32 to FP16 that picture is correct thought, so yeah in that instance IPC increases are there......
I went back to the Anandtech analysis, they feel the slide is also vague enough to be that the IPC is not clear enough and may be packed maths.
http://radeon.com/wp-content/uploads/2016/08/Polaris-Tech-Day-Architecture-Final-6.24.2016.pdf
You are only referencing PC and foregoing the greater share when considering consoles. Like it or not Consoles still have a huge impact on API and the groundwork for most games ( ie: game is made for console first ).
, another AMD slide that can be thrown in the toilet because it really doesn't show anything meaningful. Man I am beginning to hate how AMD presents information that is no information at all. speaking more to now not opengl. Called a parallel. I akin it a lot to ENB. The inventor is world renowned for his work, as well he should be, but he is an absolute ASS and an avid Nvidia fanboy. Therefore those of us with AMD hardware have to put up with the inefficiencies if we want what it brings ( I don't, I just use the memory patch ). This is akin to a lot of software out there right now, inc VR. They favor Nvidia because that is unfortunately what those writing it use. And sometimes, or even most, the writer is an ass and codes only for Nvidia, AMD be damned.
OpenGL has been under control of Khronos Group since 2006, that is plenty of time and iterations for it to be under control of a broad committee beyond what you feel is the influence of Nvidia.
That depends on how you measure memory. No reason the cards couldn't have a secondary pool like SSG. Vega 11 in theory releases with Snowy Owl APUs at which point it could be valid to add in the entire system memory capacity/bandwidth to the card for textures.
HBCC looks more like a memory manager than a memory controller. A controller capable of tracking a large number of buffers and managing them far more efficiently than would be possible with software. Games do demonstrate a performance difference in how well memory is managed and AMD listed ~50% memory as not being actively used in current games (may have been a worst case scenario, they didn't specify). Vega10 was mentioned to have 32x PCIE3 lanes by an engineer. A 32x PCIE slot is theoretically possible with the standard, albeit a bit long. In the case of the APUs (Snowy Owl/Vega11? and Naples/Vega10/11) there's no reason that traditional PCIE limit will still exist. An integrated part would use Infinity/xGMI and be more configurable. A dual package product theoretically would be 8x (16x slot / 2) to each chip then 24x lanes between without a bridge for a shared pool. A discrete card potentially with 16x lanes idle or to a secondary pool on the board. A few more memory chips for a premium part wouldn't be unreasonable or overly expensive. $50-100 more and adding 16-32GB DDR in addition to HBM2 wouldn't be unreasonable.
All the graphics that have leaked out always had a CPU to GPU interconnect on the APUs that was sufficient to accommodate all system memory bandwidth. There shouldn't be any other component connectors involved. The GPU/APU has it's own limited high performance VRAM pool then some form of secondary storage for textures which won't require all the bandwidth of ROPs in a reasonably efficient system. As I mentioned in that post, a dual Vega10 in theory can accommodate 24x lanes just to send data back and forth with reasonably low latency. An APU with Infinity between CPU and GPU I'd expect to be able to scale that bandwidth to whatever is required with even better performance than PCIE. So even a mid range APU would have 4/8GB(?) HBM2 in addition to whatever system memory could provide that isn't constrained by a connector. A Vega10 APU would have 32x PCIE3 lanes connecting it to the CPU, that should be more than sufficient for overflow at 32GB/s. The xGMI or other link should outperform that as the connection is extremely short existing over an interposer.
There's no requirement that the SSG tech uses a hard drive of any type. It's simply block IO on whichever controller they choose to connect via PCIE. There's a 128Gb/s fibre channel spec that lines up rather nicely with 16x PCIE3. That seems likely for the datacenter. They could build a custom NVMe setup or make a ramdrive. DDR3 for a cheap secondary pool would be reasonably low latency and respectable bandwidth if they went that route.
Far easier to just make a bigger APU to start with unless they want variably configured consoles. Consoles likely have the chips mounted to the board without a socket as well. I wouldn't be surprised if we see future APU systems where the APU is fixed to a SFF motherboard with a chassis designed around it.
Keep in mind AMD created the SSG because going through the CPU to access storage of even system memory was still problematic. They had demos showing the benefits of a dedicated drive. I'd expect those benefits to help that stuttering situation with lower latency, never mind the obviously increased bandwidth.
Although that was comparing to SSD storage and loading and not system RAM, developers could do much more with system RAM with regards to creating a more dynamic unified memory pool espcially where people have 16GB or 32GB but there is no incentive in same way for the developers to use VRAM efficiently.
I was thinking CPU cores in their GPUs. Effectively an APU but the other way around