Another 6 months before VEGA?

AMD already stated they will be using 8 gb 2 stacks for those.....

Why would they need to change anything for those they can use the same interposer, same everything just use 8 gb stacks instead of 4, its much easier and cost effective for them.
 
razor1 said:
AMD already stated they will be using 8 gb 2 stacks for those.....

Why would they need to change anything for those they can use the same interposer, same everything just use 8 gb stacks instead of 4, its much easier and cost effective for them.
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4x4GB may be more cost effective and easier to cool than 2x8GB. And the possibility of 4x8GB if they really wanted to go there. Limited run 8Hi stacks are likely far more expensive than 4Hi. Possibility enough to offset other costs, but can only speculate on that.
 
well there are no 8 hi stacks yet, that I know of so just have to wait and see how they do it.
 
Syphon Filter said:
It's been going on for what? The last 4 years? Maybe 5? When was the last time they could REALLY go toe-to-toe? Genuine question.
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I think when they launched the 5870 and sites like Hardware Canucks were claiming we should wait for the half year until they got their GTX 480's out the door (which were shitty cards anyhow) was last time this situation was reversed. And by then anyone who had bought a 5870 had made the card cost back in Bitcoins anyhow.

But yeah, that was eight years ago. ish.
 
I like the cut of your jib sir.

few things.

firstly, briefly, fyi, tellingly imo, amd have quietly changed to using the term cache for vram/page frame... I suspect it reflects how they see the new reality. its not gpu ram per se. its just part of a a cascading set of pools of cache - like l1/2/3 etc.

What excites me about the hbcc, is the notion of huge memory, even ~unlimited - 512TB (for vega anyway, but i suspect also for zen.

as in this trial run ~ a year ago:

https://www.google.com.au/url?sa=t&...u.html&usg=AFQjCNGdgsE5VtPWewV5oNn2fl6NewgP-w

all is in place for amd to deliver a killer feature nobody knows they want - yet. Its never been possible before.

Noting, that 8GBps seems doable from a tweaked, striped , pair of nvme ssdS glued on the vega fabric.,

Then, the hbcc, after exhausting gpu ram, falls back to larger/cheaper/slower pcie bus bound system ram.

AND,

if that limit is exceeded

has a further fall back to the above ~8GBps 1TB ssd raid array, dedicated to the independent gpu bus.

even the bottom rund doesnt sound so bad considering many say 8 lanes (8GBps) is sufficient for a gaming gpu.

The cherry on top of all this is, that the nvme and vram are on the vega bus, which is on the zen fabric, so multiple cpu & gpuS on a mcm like epyc, will share these cache pools using fabrics separate and huge interconnect bandwidth.

a further option for such powerful systems wouldb be a further striped nvme array on the system.

The fun part, in conclusion, is i imagine monster versions of the humble apu, kicking sand in nvidias face.

from leaked chip shots of raven ridge, we know that version of vega is similar size to the zen 4 core.

so a variant of the epyc mcm (can use 8 such processors) used as such an apu, & allowing space for nvm & onboard hbm2, could be 8 core & 4 gpu.
 
ecmaster76 said:
We've been able to increase performance considerably from PCIe gen 1 to gen 3 with most of the major changes being on the endpoints. If AMD designed the Infinity Fabric protocol to run within the same clock and power constraints as PCIe gen 3 then there would be no cost or complexity increase to the consumer parts.
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in newb speak, i have seen slides showing fabric can use ~lanes to talk either pcie3 or fabric over the lanes within fabric.
 
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