AMD Ryzen Threadripper Delidding

theplaidfad said:
Waiting for Intel do drop a response before enabling the other two dies and renaming it "Butt-Hurter"?
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Question is, are they laser cut, or could they potentially be unlocked like in the old Phenom II X2's which were actually X4's?

My favorite overclocking in the modern era was when I bought my ex stepson a dirt cheap Phenom II X2 in ~2009 or 2010 (cant remember) and we unlocked it to 4 full cores, and overclocked it to 4.2Ghz.

It was getting a kickass system for not very much money.
 
It seems odd to populate all four dies and then disable two. It would have to be the same two disabled all the time which is not going to allow selling an Epyc with failed cores as a consumer part. If it is the case, I would have rather AMD pulled an Intel and used a smaller cheaper socket for the HEDT parts.
 
cactus said:
It seems odd to populate all four dies and then disable two. It would have to be the same two disabled all the time which is not going to allow selling an Epyc with failed cores as a consumer part. If it is the case, I would have rather AMD pulled an Intel and used a smaller cheaper socket for the HEDT parts.
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Its possible they have some clever trick to make it work for any of the dies. Are we dead sure that they aren't 4x 4c enabled dies with 1 memory channel enabled each?
 
ecmaster76 said:
Its possible they have some clever trick to make it work for any of the dies. Are we dead sure that they aren't 4x 4c enabled dies with 1 memory channel enabled each?
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If it is, they wouldn't admit to it. He says in the video that AMD confirmed that 2 cores were disabled. Why would they lie about that though?
 
cactus said:
It seems odd to populate all four dies and then disable two. It would have to be the same two disabled all the time which is not going to allow selling an Epyc with failed cores as a consumer part. If it is the case, I would have rather AMD pulled an Intel and used a smaller cheaper socket for the HEDT parts.
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I always found that weird, but maybe they just dont have a contract or enough money to do such contract with DF.

Maybe in a year or so, if they make enough money, they might have some breathing room with either more money available or perhaps, a more modular design in Zen 2.
 
Might indeed be an engineering sample.

Elsewhere, people speculated that the initial Threadripper production run is actually Epyc. Would be interesting to see if someone dared to install this CPU into a socket SP3 mobo. Like the initial batch of RX480 4GB reference cards were actually 8GB models with the extra memory disabled via VBIOS.
 
So are retail cpu's using solder? If so why is intel being so cheap using paste.
 
if the 1700-1800x has 24 PCI-E lanes, then to get 64, you would need 3 dual CCX at least? Stick a 4th one in and use only silicon that would have been for a 1400 with one failed memory channel and BOOM, you have a Thread Ripper. I'm thinking AMD is not getting the such high quality yields that their fanboys are raving about and this is a pretty smart-ass way to get top dollar for an otherwise crappy silicon. Anyways the proof in in the pudding. If we can measure PCI-E latencey, I'm guess it is going vary since some lanes will have to traverse the Infinity fabric.
 
ecktt said:
if the 1700-1800x has 24 PCI-E lanes, then to get 64, you would need 3 dual CCX at least? Stick a 4th one in and use only silicon that would have been for a 1400 with one failed memory channel and BOOM, you have a Thread Ripper. I'm thinking AMD is not getting the such high quality yields that their fanboys are raving about and this is a pretty smart-ass way to get top dollar for an otherwise crappy silicon. Anyways the proof in in the pudding. If we can measure PCI-E latencey, I'm guess it is going vary since some lanes will have to traverse the Infinity fabric.
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That makes no sense at all when looking at the diagram of epyc where EACH CPUdie has 64lanes. Not the least of which at this moment the delidding was likely an engineering model.
 
RogueTadhg said:
I'm getting all moist thinking about it.
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I believe the technical term is "SPLOOSH".

Flexion said:
Hahaha. you beat me to it. it'd be funny if all core clusters could be activated by tracing with a pencil. XD
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You joke.... but we all want this to be true! I have fond memories of my old T-Bird, a magnifying glass, and a mechanical pencil. Makes me want to fire up the ol' Urban Terror Q3 mod.
 
JustReason said:
That makes no sense at all when looking at the diagram of epyc where EACH CPUdie has 64lanes. Not the least of which at this moment the delidding was likely an engineering model.
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Which diagram good sir?
Everything I have seen neither confirms nor negates anything I've postulated. Nothing I have read suggest each die has 64 lanes either.
 
ecktt said:
Which diagram good sir?
Everything I have seen neither confirms nor negates anything I've postulated. Nothing I have read suggest each die has 64 lanes either.
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you should read more then before making statements as if you do in fact know. I don't have the discussions saved but take this one step further... how many lanes does EPYC have with 4 dies? 128... So how does your asinine theory hold up here? It doesn't. And again he is likely delidding an ES TR so doubtful TR has 4 dies with 2 disabled.
 
If he had one of these, then he would not have fried his CPU.

tbredbshim.jpg
 
ecktt said:
if the 1700-1800x has 24 PCI-E lanes, then to get 64, you would need 3 dual CCX at least? Stick a 4th one in and use only silicon that would have been for a 1400 with one failed memory channel and BOOM, you have a Thread Ripper. I'm thinking AMD is not getting the such high quality yields that their fanboys are raving about and this is a pretty smart-ass way to get top dollar for an otherwise crappy silicon. Anyways the proof in in the pudding. If we can measure PCI-E latencey, I'm guess it is going vary since some lanes will have to traverse the Infinity fabric.
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The zen core actually has 32 pcie lanes, but not all are enabled. Some good info here https://forums.anandtech.com/threads/zeppelin-ryzen-i-o-capabilities.2511227/
 
JustReason said:
you should read more then before making statements as if you do in fact know. I don't have the discussions saved but take this one step further... how many lanes does EPYC have with 4 dies? 128... So how does your asinine theory hold up here? It doesn't. And again he is likely delidding an ES TR so doubtful TR has 4 dies with 2 disabled.
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I simply asked for that diagram you referred to which you failed at. The single die or 2 CCX (R1200-1800X) are advertised as having 24 PCIE. You have provided no proof that each EPYC die has 64 pcie lanes per CCX pair to quantify any argument. The fact that the entire package has 128 can only imply each CCX pair has at least 32.
You can continue to argue with yourself if you want but thanks for nothing in the way of evidence or even a good theory but I enjoyed a good laugh.
 
ecktt said:
I simply asked for that diagram you referred to which you failed at. The single die or 2 CCX (R1200-1800X) are advertised as having 24 PCIE. You have provided no proof that each EPYC die has 64 pcie lanes per CCX pair to quantify any argument. The fact that the entire package has 128 can only imply each CCX pair has at least 32.
You can continue to argue with yourself if you want but thanks for nothing in the way of evidence or even a good theory but I enjoyed a good laugh.
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I don't have every piece of data saved nor do I wish to hunt for the info. And as you finally see above you were in fact WRONG. You made an assumption and poised it as fact. I told you, you were wrong and lo and behold you were and what I stated was in fact correct.

The fact that lanes can be disabled is all i was basing my guess with.
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if the 1700-1800x has 24 PCI-E lanes, then to get 64, you would need 3 dual CCX at least? Stick a 4th one in and use only silicon that would have been for a 1400 with one failed memory channel and BOOM, you have a Thread Ripper. I'm thinking AMD is not getting the such high quality yields that their fanboys are raving about and this is a pretty smart-ass way to get top dollar for an otherwise crappy silicon. Anyways the proof in in the pudding. If we can measure PCI-E latencey, I'm guess it is going vary since some lanes will have to traverse the Infinity fabric
Click to expand...

You were basing your guesses on having only 24 per 8cores not the ability to turn them off as has been done for decades. And therein asserting that TR would need 4 dies to achieve 64PCI-E lanes.

Again had you been up on all thing Zen you would have never made those assumptions, as I pointed out.
 
JustReason said:
That makes no sense at all when looking at the diagram of epyc where EACH CPUdie has 64lanes. Not the least of which at this moment the delidding was likely an engineering model.
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ROFL. You better tell it to your 64 PCIE lanes per die.
 
So if a Threadripper is a gimped Epyc, Does that mean it may be possible to use an Epyc on a Threadrippper MB?
 
No surprises here.. clearly AMD under lisa su is going for very simplified product lines.. Can the do hedt with 4 ccx cores of half cpu half vega chips.. that would be a crazy cpu or apu more like.
 
Deathlizard said:
So if a Threadripper is a gimped Epyc, Does that mean it may be possible to use an Epyc on a Threadrippper MB?
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Im betting that will be the case. No loss for AMD, plus im guessing you won't get the same warranty as in server parts.
 
ecktt said:
ROFL. You better tell it to your 64 PCIE lanes per die.
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really? He told you there are 32 per 4core not 8core. therefore 64 per 8core = CPUdie and there are 2 of them in TR @128 lanes with 64 reserved for communication between each.
 
Burticus said:
I believe the technical term is "SPLOOSH".



You joke.... but we all want this to be true! I have fond memories of my old T-Bird, a magnifying glass, and a mechanical pencil. Makes me want to fire up the ol' Urban Terror Q3 mod.
Click to expand...

Ah the T-Bird that you can cook an egg on? Or the T-Bird that would just die if your cooler or fan failed for any reason cause it didn't have thermal protections?
 
michalrz said:
Urban Terror (4.3.1?) is a standalone game now. What if I told you I was -=UrF=- Dave.
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I think I remember reading it was a standalone thing now, but back in the T-Bird days of 2002, it was a Quake 3 mod. And we played it with Geforce 2 and 3's (think I had a GF 3-TI back then)
 
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