z-RAM cache

wizzackr

[H]ard|Gawd
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you gotta love how quick new stuff is on the horizon in the hardware arena :D - and yeah, I know it's a lot of "could" and "sometime-in-the-futures" in that article :p
 
Seems to fit well with the K10 timeline, looks interesting but I can't really visualize the major benefits just yet.
 
Here's a few more tidbits.

“The dramatic increase in density offered by ISi’s Z-RAM embedded memory can enable much larger on-chip microprocessor cache memories resulting in improved performance and reduced I/O power consumption,” said Craig Sander, corporate vice president of technology development at AMD, EETimes web-site reports.

Looks good :D
 
Looks like they're taking advantage of the fact that with SOI if a gate held in an 'ON' state for a period of time, the body around the gate will develope a charge. By applying a charge on the drain then you can develope a body to source current to check for a charge on the body (in much the same way traditional DRAM reads from its capacitor).

There would seem to be some major engineering challenges ahead for Z-RAM, but there could be some major payoffs as well.
 
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