Why LGA?

[FoolOnTheHill]

I've been seeing all the Prescott articles on the net, and I've been seeing plenty about the new processor packaging, LGA, but I dont understand why they're making the transition. What are the advantages with the new packaging? I would expect a bent pin to be much more fatal when it's on the motherboard instead of the CPU. Anyone have reasons or links?

 

[Big Worm]

I believe its for better contact between the pads and socket.

I think...

also I would imagine one of there costs is making all tose gold plated pins, the pads would probibly be alot cheaper.

I like the idea cause 10 bent pins on a northwood is a real pita.

 

[USMC2Hard4U]

Its because the processor is becomming smaller and there is too many pins to fit on it, so they put it on the mobo instead.

 

[mtbaird]

what exactly are yall talking about?

 

[SanGreal]

Originally posted by mtbaird
what exactly are yall talking about?

http://www.anandtech.com/cpu/showdoc.html?i=1943

 

[CentronMe]

The Prescotts are going to move to a new type of packaging in a few months called LGA. They along with Tejas (P5) will use socket LGA-775. Basically the pins are on the motherboard and on the bottom of the CPU are contact pads. Look at Anand's writeup for pics and more info.

 

[0ldman]

LGA is suppose to be cheaper to produce with less signal and voltage loss due to the interconnects.

This was the statement about a year ago...

 

[rayman2k2]

Originally posted by CentronMe
The Prescotts are going to move to a new type of packaging in a few months called LGA. They along with Tejas (P5) will use socket LGA-775. Basically the pins are on the motherboard and on the bottom of the CPU are contact pads. Look at Anand's writeup for pics and more info.

Tejas is not Pentium 5, Nehalem, the one after Tejas, is Pentium 5...

 

[shaihulud]

funny how sometimes when intel says it is meant to be cheaper it ends up being more expensive e.g. sec. anyway, as people posted here, there is a reduce in cost to intel and the motherboard manufacturer due alone because of the pins. no more nickel/gold plated pins for intel. motherboard companies have less trace mask to lay (if i remember correctly). this also creates a better single path which is needed for better frequency scaling.

i still think following intel's normal upgrade path costs, cost savings are not going to be seen for a while.

 

[VVVVVVVVVVVVVVVI]

SEC WAS cheaper than the PPro, which had two seperate chips (cpu and cache) connected together in one package. The yields of the Pentium Pro were lower and the packaging costs were higher than SEC.

It was a better option than the seperate COAST or having no cache at all (like the Celerons).

 

[trudude]

Originally posted by rayman2k2
Tejas is not Pentium 5, Nehalem, the one after Tejas, is Pentium 5...

What makes you say that? I thought that the Tejas would be a P5 and that Nehalem is the improved version of Tejas. The Tejas is such a new radical design with the stackable design of the chip that I would think that it would be the P5. I also heard that the Nehalem was just a Tejas with a 4Ghz BUS. Anyone remember reading about this?

 

[trudude]

Originally posted by CentronMe
The Prescotts are going to move to a new type of packaging in a few months called LGA. They along with Tejas (P5) will use socket LGA-775. Basically the pins are on the motherboard and on the bottom of the CPU are contact pads. Look at Anand's writeup for pics and more info.

I thought that the Tejas was going to be BGA using ball bearing interfaces on the mobo to accomodate the stackable cpu design.

 

[chrisf6969]

LGA also helps keep the space small with so many pins.

When you have that many pins in that small of an area things get tight. And you cant decrease the diameter of the pins with out making them too weak. (easily broken) flat pads are a lot more durable and easier to pack in a tight space.

Imagine packing 700+ sky scrapers in a small area as opposed to 700+ short buildings.

 

[shaihulud]

oh, i know all about the pentium pro. it was sort of doomed from the beggining. the fabrication process at the time was not ready for the pro. one mistake made the whole chip bad (cache and processor). so the move to a dual in line bus [dib] for cache with the sec model was used. but that proved not to be that beneficial as socketed chips after all. the move was made back after the fabrication process was beneficial in yields. when in that perspective the move was cheaper. but i was looking long run. in this perspective it was not since it proved to be a temporary move, specially when compared to the years of socketed cpu's. i do also remember reading a whitepaper at intel complaining of cost for sec (this was right at the time for the organic grid array p2-400). the major complaint was for the heatspeader. all that metal was consider a waste/costly and also a preventer of heat disippation. which lead to cartridge revision. to reduce cost again.....funny

remember the original celeron had 128k l2? they became very popular and performed better than the 512kdib p2 at the time.

you can look at it from this perspective to. if there was such a good cost savings then how come we didnt get a better reduction in consumer costs till the athlon came out?

coast was just a failed attempt by intel for standardization of cache

 

[Koz]

775 pins is harder to make than 775 contact points. It may be possible to do (Athlon FX) but they've probably decided it was a better idea to just switch packages. Also, its probably more durable. How many of you know someone who's bent pins before. Just having contact points makes the chip less likely to have physical damage done to it.

 

[VVVVVVVVVVVVVVVI]

Originally posted by trudude
What makes you say that? I thought that the Tejas would be a P5 and that Nehalem is the improved version of Tejas. The Tejas is such a new radical design with the stackable design of the chip that I would think that it would be the P5. I also heard that the Nehalem was just a Tejas with a 4Ghz BUS. Anyone remember reading about this?

Tejas is the same 'Netburst' core as the P4. Nehalem is an all new next gen design.

IIRC, that whole stackable design was some rumor started by Inq (?). I can't remember.

Anyway, what Intel names their chips is something the marketing department comes up with. I doubt they know for sure at this point what they are going to call Tejas. What gen the core is hasn't mattered in the past (PPro-->PII-->PIII).

Originally posted by shaihulud ...but that proved not to be that beneficial as socketed chips after all. the move was made back after the fabrication process was beneficial in yields. when in that perspective the move was cheaper. but i was looking long run. in this perspective it was not since it proved to be a temporary move, specially when compared to the years of socketed cpu's...

So, in other words, SEC package was cheaper than then PPro package. Once the process shrunk, and Intel was able to integrate cache directly onto the die, they returned to sockets which enabled an even greater cost savings. That doesn't really meld with your original idea that SEC was more expensive. It was more expensive than the unavailable at the time process shrink which enabled on-die cache.

remember the original celeron had 128k l2? they became very popular and performed better than the 512kdib p2 at the time.

I can't remember that far back in time, but as I recall the Celerons were popular due to their overclocking ability, especially because of the on die cache. The P2's were faster in most apps, despite the slower larger cache, but were held back by the seperate cache when overclocking.

But, I can't really remember that far back.

you can look at it from this perspective to. if there was such a good cost savings then how come we didnt get a better reduction in consumer costs till the athlon came out?

I can't remember that far back with regards to cost either, but who says they have to pass savings onto the consumer?

Besides, I think they were, since the PII was cheaper than the PPro, but still had close performance in most apps (not counting the increased clockspeed) despite the seperate slower cache.

coast was just a failed attempt by intel for standardization of cache

COAST was certainly not a failed attempt. It was a standard feature on motherboards at the time.

 

[trudude]

I do not think that the CPU in the Anandtech articles are Tejas. I think that they are just the new package for the Prescott. I think that the Tejas will be using BGA for sure....

Oh yeah...and I can't remember where I posted this but I mentioned on a forum that I thought that they were gonna start using a brand new package for RAM chips for DDR-II and I was told that I had no clue what I was talking about....

I told them that the package would be the Wafer Level Chip Scale Package similar to the chips found on GeIL Golden Dragon memory and on video cards because of its low noise properties...

Seems I was right about that...

 

[eviltommy]

 

[shaihulud]

it is hard to see the big picture here. the dual in line bus is what created the reduced cost for the p2. there was less waste with the yields. the pentium pro had a big disadvatage with error. error on the die either cpu or cache made it entirely bad. the pentium 2 you were able to test both before final fabrication. but the cartridge was very expensive to make and was revised because of it. the sec also gave intel the ability to make it hard for motherboard manufacturers to streamline thier products. build sec 1's or sockets 7's? have you ever notice how amd keeps the product package close to intels? that is especially during the athlon times.

some savings came also from the business model that the pentium pro was used for. it was mainly for non-entry workstation and server based. this segregation allowed, if you will, the increase costs of it. the only real advantage was beyond 2 multiprocessor support and the increased cache later given. when the pent pro was benchmarked there was not that much difference between it and the p2 (almost the same core after all) but! it had more than 2 multiprocessor support and was less expensive and performed better,at the time, than non x86 alternatives.

is this starting to make better sense? it was not the sec that made it less expensive the sec was the physical deliverly of the item that is all. intel commented on the waste and cost of it. it was the over all architectural changes that was the p2 that seperated and decrease its cost when compared to the pentpro.


VVVVV~V, you contradict yourself here: I can't remember that far back in time, but as I recall the Celerons were popular due to their overclocking ability, especially because of the on die cache. The P2's were faster in most apps, despite the slower larger cache, but were held back by the seperate cache when overclocking.

especailly the on die cache? yes that was what i said. the cache with the very first version of the celerons was on die. all though it was 128k the advantage was tremendous over the p2 even with 512k running at half the clock of the processor. the celerons were released with slower clock speeds and fsb speeds, but still had advantages. this is what lead to the cache-less celerons. no one was purchasing the p2 and intel was losing money.

about coast: http://www.computer-dictionary-online.org/?q=Cache On A STick

do i need to make myself anymore clear than that????

 

[VVVVVVVVVVVVVVVI]

Originally posted by shaihulud
snip...

is this starting to make better sense?

Which was all originally stated in a single line in my first post:

"The yields of the Pentium Pro were lower and the packaging costs were higher than SEC."

it was not the sec that made it less expensive the sec was the physical deliverly of the item that is all. intel commented on the waste and cost of it. it was the over all architectural changes that was the p2 that seperated and decrease its cost when compared to the pentpro.

Which allowed for the PII to be cheaper, NOT more expensive like you stated in your original post. We are going in circles here, and you are just backtracking away from your original statement, which was:

funny how sometimes when intel says it is meant to be cheaper it ends up being more expensive e.g. sec.

It was not more expensive than what it replaced.

VVVVV~V, you contradict yourself here: I can't remember that far back in time, but as I recall the Celerons were popular due to their overclocking ability, especially because of the on die cache. The P2's were faster in most apps, despite the slower larger cache, but were held back by the seperate cache when overclocking.

especailly the on die cache? yes that was what i said. the cache with the very first version of the celerons was on die. all though it was 128k the advantage was tremendous over the p2 even with 512k running at half the clock of the processor. the celerons were released with slower clock speeds and fsb speeds, but still had advantages. this is what lead to the cache-less celerons. no one was purchasing the p2 and intel was losing money.

I didn't contradict myself. I stated the Celerons were more popular because they overclocked better due to the on-die cache, not because they performed better. IIRC, the PII with the larger half-speed cache still outperformed the Celeron in most apps.

The very first Celerons didn't have any L2 cache at all.

about coast: http://www.computer-dictionary-online.org/?q=Cache On A STick

do i need to make myself anymore clear than that???? [/B]

You said COAST was a failure. A popular cache system that was on a large number of Pentium class motherboards was not a failure, and your link does nothing to say otherwise. Maybe you are getting into some sort of silly argument over vendors not following the specifications of COAST, but that is an entirely irrelevant semantical argument . Call it whatever you want, but cache on a stick, be it the Intel standard or not, was not a failure. Even if it was, it has nothing to do with my original reason for mentioning it as a possible if improbable alternative to SEC, especially since I specifically said SEC was a better option for the PII.

This is a really ridiculous conversation. SEC was NOT more expensive, bottom line, end of story, thanks for posting.

 

[Tedinde]

Originally posted by FoolOnTheHill
I've been seeing all the Prescott articles on the net, and I've been seeing plenty about the new processor packaging, LGA, but I dont understand why they're making the transition. What are the advantages with the new packaging? I would expect a bent pin to be much more fatal when it's on the motherboard instead of the CPU. Anyone have reasons or links?

Why?? to sell us all new boards!!!

 

[Big Worm]

Originally posted by VVVVVVVVVVVVVVVI
This is a really ridiculous conversation. SEC was NOT more expensive, bottom line, end of story, thanks for posting. [/B]

It wasn't SEC, it was SECC, I think.

SECC at the time was cutting costs due to the cache being off-die.

They found the SECC packaging was infact more costly on CPUs with on-die cace (aka celerons with cache and PIII)

Your right though, the SECC packaging was cheaper with the Pentium 2 with off die cache.

Same thing with AMD, they found the SECC type packaging a better cost solution witht he old athlons with off die cache (man that cache sucked) Once going to on-die cache... viola socket 462.

In other words I agree,

 

[shaihulud]

secc, oops, forgot the cartridge part. i guess you get the picture to big worm. the secc was not really what made the p2 cheaper but the dual in line bus feature that allowed the processor to have a separate half speed cache (this is where the term front side bus came from and also the segragation from the pentium pro). the single edge contact was needed to fit the paradigm of the processor. the packaging for it was wasteful and redesigned.

the packaging cost for the pro was not expensive the die was expensive. most of it becamea waste before it even hit the final production. this is another of the seperation cost difference between the two.

amd did not follow the secc design becasuse of cost. they did it so that motherboard manufacters didnt have to shift thier fabs. Also it gave simularities to an intel product giving it a more adoptable feeling to the consumer. this is very simple to see. it was even pointed out with many technical sites. if amd did not do this, then adaptation would have taken longer for slota.

my statement is simple. intel said the single edge contact cartridge will make the pentium2 less expensive to make. it was not after all (think big picture). it was the over all features of the pentium 2 that gave the cost reductions.

in the snip you made of my stament: remember the original celeron had 128k l2? they became very popular and performed better than the 512kdib p2 at the time. then you go on to say I can't remember that far back in time, but as I recall the Celerons were popular due to their overclocking ability, especially because of the on die cache. so, i replied back the way i did due to the misrepresentation of your point.

coast was not adopted fully. this is very much like rambus. it was around but not succesful-failed attempt of standardization. the motherboard manufactures did not like it do to various reasons.

 

[VVVVVVVVVVVVVVVI]

It was originally called SEC. Intel later called it SECC. Both are correct terms.

http://www.intel.com/design/quality/icstorage/trans_secc.htm

shaihulud, you are just playing silly games to get out of a mistatement you made:

funny how sometimes when intel says it is meant to be cheaper it ends up being more expensive e.g. sec.

Is wrong. What kind of person are you that you have to make long posts regurgitation information most people already know in order to avoid admitting you were wrong?

I said:

SEC WAS cheaper than the PPro, which had two seperate chips (cpu and cache) connected together in one package. The yields of the Pentium Pro were lower and the packaging costs were higher than SEC.

Which is what you have been trying to say for, what 3 or 4 posts now? Something I already said? In my first post? You are trying to magically seperate the statement I made into two parts, and ignoring the more important part, when if fact it is one statement.

Since you are being dishonest and trying to mischaracterize my statement by ignoring a key portion of it and taking it out of context, allow me to rephrase it:

SEC WAS cheaper than the PPro, which had two seperate chips (cpu and cache) connected together in one package. The yields of the Pentium Pro were lower

Enough already. You don't need to make anymore long worthless posts about stuff I already know that I already briefly mentioned in my first post.

And you are playing more games regarding the whole COAST subject. Not only was it on a large number of motherboards for several years as a regular feature, your argument has absolutely nothing to do with the original point of me mentioning it. It is irrelevant if Intel had decided to use some sort of cache on a motherboard feature, be it coast or not.

 

[CentronMe]

This is getting old and very off topic...

 

[shaihulud]

i think it is simple comprehension. i said intel will often say something is less expensive and it is not e.g. (for example) sec. you said the sec is cheaper than pentium pro. you meant that pentium 2 is cheaper than pentium pro. which is what i affirmed (the attributes). cause sec was not that inexpensive and was revised cause of it (along with other various reasons i have regurgitated). this was about the land grid array packaging and i was making comparisons to the sec cartridge packaging. simple.



edit note: not one single post i made was i an ass to you and everyone here. i would suggest you reciprocate not to just me but everyone here in this forum.

 

[Big Worm]

The FACT of the matter is this,

Intel will always go for the cheaper packageing.

Its besides the point if the packaging they choose costs them more until 6 months down the road when they can utilize it a bit better. Either way they look at the big picture, it will be cheaper for them to start LGA now then keep the current design going longer and end up costing much more when its critical for them to change.

They will not loose money period.