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Why a reducton in L2?

C

commissioneranthony

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I was just reading an article from notebookcheck:
http://www.notebookcheck.net/Newsentry.153+M514798e83a0.0.html
and noticed that the L2 cache size of the I7's are incredibly small, while the L3 cache size is incredibly large. Is this a trend or something? why would they decrease L2 cache size so drastically when for years they've been trying to ramp up L2 cache size? is L2 going to become second nature as has L1 cache? Why not make a CPU with a moderate amount of L1, L2 and L3 cache per core? Say like 1 mb per core or 4 mb pooled cache per core if Intel wants to go chared cache. If anyone can explain this anomaly that would be great.
 
Well several reasons.

With the Core 2 series, Intel was using a Front Side Bus and keeping the Cores coherent through the FSB was a challenge due to the restrictions imposed in terms of bandwidth. Therefore Intel opted to use a large shared pool of L2 cache as a means of communication between the Cores. Only when using a Quad core (two dual cores) do you really tax the front side bus.

With Intel moving to a point to point interconnect (QPi) there was no reason to have such a large cache (also the processor was already quite large in the transistor and physical size areas).

So Intel cut the cache.
 
Is this a trend or something?
Click to expand...
No, it's just the way the new cpu architecture was designed.
why would they decrease L2 cache size so drastically when for years they've been trying to ramp up L2 cache size?
Click to expand...
Again, it's a new architecture, it operates differently. Intel's engineers structured the cache as they deemded necessary for the way the CPU processing data. It may have a lot to do with the integrated memory controller and the insane system memory bandwidth the i7 architecture has gained, but that's only a guess.
Why not make a CPU with a moderate amount of L1, L2 and L3 cache per core? Say like 1 mb per core or 4 mb pooled cache per core if Intel wants to go chared cache.
Click to expand...
Because the engineers who designed the CPU, looked at their transistor count budget, and designed the optimal amount of each memory based on how the CPU operates. Memory(Cache) takes up a lot of transistors which impacts power, heat, cost, size, and manufacturing yields.
 
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