• Some users have recently had their accounts hijacked. It seems that the now defunct EVGA forums might have compromised your password there and seems many are using the same PW here. We would suggest you UPDATE YOUR PASSWORD and TURN ON 2FA for your account here to further secure it. None of the compromised accounts had 2FA turned on.
    Once you have enabled 2FA, your account will be updated soon to show a badge, letting other members know that you use 2FA to protect your account. This should be beneficial for everyone that uses FSFT.

What limits gpu die size?

T

tybert7

2[H]4U
Joined
Aug 23, 2007
Messages
2,763
I ask because I was looking at a graphic for polaris 10 and 11 over on wccftech (so we know it must be true) showing off the relative sizes.

AMD 14nm FinFET Polaris GPU Size Leaks Out - 232mm² Large Die

I don't know if they were to scale, but assuming they were, I used microsoft paint to stitch together the smaller die to see what size it would take up.


Here is what I found, placed right next to polaris 11.




E1QqnsE.png



Assuming the two die sizes are to scale, it looks like polaris 11 is right around 4 times the area of polaris 10.


And assuming polaris 10 is the gpu that was slated to have a 232mm^2 die size... then does that imply polaris 11 could have a ~908mm^2 die size ?!?!??? (for reference, the largest nvidia titan dies were in the 600 and change square mm range)



It seems like that would be crazy large, larger than anything ever reported. So it's probably not the case but... Could that even be done? What limits die size?


I remember hearing that the reason they did not build fury x even larger was that they were constrained by lithography. I heard that on a Scott Wasson techreport podcast. But I have NO CLUE what any of that means. Is that still a constraint with the 14nm die shrink? Is it the same constraint or can they go larger now?


Is it that a die that size would get WAY too hot to deal with? That constraint might be solvable when you consider that polaris is supposed to be a much more efficient architecture coupled with the accumulated power savings gains of hbm over gddr5.


So.. is a die that large possible? And if not, what limits it?
 
The larger the die size, the higher the probability of defect. This goes up the newer the process node is. So don't expect big dies on release day, just like there was no Titan or R9 290X when the 28nm generation was released.

In addition, there's a maximum size dictated by the process node reticle limit (there is a maximum mask size they can run through the automated machinery). Fury X ran up against this, which according to the press information is the reason they stuck with 64 ROPs.

If they're releasing a die 232mm² as Polaris 10, then I'd expect twice the die for Polaris 11.

Much like Fiji is 2x Tonga, with HBM added!
 
Last edited:
Well if you read the article and what Raja Koduri hinted repeatedly on twitter, it would seem that Polaris 11 is the 232mm^2 chip and Polaris 10 with only around 60mm^2 would be the entry level product, with performance that should roughly be equal to current R7 360's (a bit below, but closer to it than to the 350). That is because Mr Koduri seems to hint at a 2.5x performance of the chips vs current offerings.

Of course this is all just a supposition until we get Polaris later in the year, so any guess is good.

Btw in the comments of the article they answered your question about what limits it, and that is the mask size of around 600mm^2 for 28nm tech and seriously doubt that they would increase it for the 14nm FF tech. (This has to do with the way chips are made with photolithography if i remember correctly, plus statistical studies that determine the likelyhood of fatal errors due to the area of the chip more than due to thermals)

edit to explain:
the 2.5x would be taken as 2.5x the area, of course that this could be wrong and the metric can be 2.5x almost anything else, with a likely candidate being power efficiency.
 
The size can also be of influence on the process. It could very well be that due to shrinking it to much the design would not perform and yields would be terrible. That there going for the "smallest" possible size is normal.
Look up that ARM news where they are gong to 28nm process you might think it is stupid but supposedly they can still gain a lot of benefits from it due to the process changes.
ARM Extends 28nm IP Leadership With Latest UMC 28HPC POPs - ARM

Some explanation
ARM Announces New 28nm POP IP For UMC Foundry
 
Revdarian said:
Well if you read the article and what Raja Koduri hinted repeatedly on twitter, it would seem that Polaris 11 is the 232mm^2 chip and Polaris 10 with only around 60mm^2 would be the entry level product, with performance that should roughly be equal to current R7 360's (a bit below, but closer to it than to the 350). That is because Mr Koduri seems to hint at a 2.5x performance of the chips vs current offerings.

Of course this is all just a supposition until we get Polaris later in the year, so any guess is good.

Btw in the comments of the article they answered your question about what limits it, and that is the mask size of around 600mm^2 for 28nm tech and seriously doubt that they would increase it for the 14nm FF tech. (This has to do with the way chips are made with photolithography if i remember correctly, plus statistical studies that determine the likelyhood of fatal errors due to the area of the chip more than due to thermals)

edit to explain:
the 2.5x would be taken as 2.5x the area, of course that this could be wrong and the metric can be 2.5x almost anything else, with a likely candidate being power efficiency.
Click to expand...


if 232mm^2 is polaris 11 that seems super small for a flagship, it has to take on the 980ti which is over 600mm^2 and though I'm sure it can best it with improvements in performance per watt, the sheer brute force die siza advantage would blunt the gap in performance. if amd does not release something larger.


Perhaps polaris 11 is like the 7970, a mid tier die size for a mid tier price in the 300-350 range to target the single most popular gpu cost segment, the 970.

And of course the smaller ~ 60mm^2 die would be for notebooks.
 
tybert7 said:
if 232mm^2 is polaris 11 that seems super small for a flagship, it has to take on the 980ti which is over 600mm^2 and though I'm sure it can best it with improvements in performance per watt, the sheer brute force die siza advantage would blunt the gap in performance.
Click to expand...


600 mm^2 at 28nm vs 232 mm^2 at 14nm ff

Also, there is a huge difference between a mature process as is the 28nm and the new 14nm ff process, there was a reason why it took a while for the 980ti to exist, a chip that is at the extreme of what is possible with the 28nm mask size.

If the 2.5x refers to area efficiency then 232mm^2 at 14nm ff process would be comparable to a 580mm^2 28nm process.


In any case like i said, this is just a game of speculation at the time being, something to keep us entertained but we shouldn't try and take it serious until we get solid info.
 
Now im worried these new GPUs are jsut gonna be shrinks/efficiency versions of what we have now. Great if you're a greeny, but i want MOAR POWER! Guess ill have to wait 2 years for the Titan/Fury of 14nm DX
 
There are many factors which limit the die size. As mentioned here the more elements packed on a die the lower the yield due to higher probability of defects. The bigger the die the less dies fit on one wafer which reduces economy of manufacturing. Bigger die equals bigger heat dissipation and there is a limit on cooling by heat transfer from the die. Taking all these factors together makes possible to calculate optimal die size. There were rumors Pascal chipss will have twice the transistors of Maxwell chips, this would suggest Pascal die would be the same size as the Maxwell die, that is 600 mm2.
 
wirk said:
There are many factors which limit the die size. As mentioned here the more elements packed on a die the lower the yield due to higher probability of defects. The bigger the die the less dies fit on one wafer which reduces economy of manufacturing. Bigger die equals bigger heat dissipation and there is a limit on cooling by heat transfer from the die. Taking all these factors together makes possible to calculate optimal die size. There were rumors Pascal chipss will have twice the transistors of Maxwell chips, this would suggest Pascal die would be the same size as the Maxwell die, that is 600 mm2.
Click to expand...
Rumors confirmed now :p insane isn't it
 
A proper paper launch of said rumor product, at least no wood screws this time ;)
 
You must log in or register to reply here.
Back
Top