What is "process type"?

[Revlt Coranier]

I was looking at processors on newegg and in the Specs section, they have an entry called "Process Type". All the processors I've seen have either "0.13 µm" or "90 nm" listed for it. What does it all mean?

(I did a search but couldn't find anything about this)

 

[umbra]

it's the level on which they are built .13 means that the traces on the cpu are 130 nanometers wide and same goes for .9. it's simply how thin the traces of the cpu are

 

[Revlt Coranier]

Ahh. Is one better than the other? What impact does this have on performance?

 

[umbra]

depends on the core which is like the design of the cpu. ie prescott is 90nm but has worse performance than a northwood 130nm because it has more gates in it's design but as far as amd is concerned right now 90nm kicks ass and overclocks like a mofo

 

[Revlt Coranier]

Thanks!

 

[Eva_Unit_0]

the process size doesn't directly affect performance at all. As stated above, all it does is say what the transistor gate width is. You could make any core on any size process, if you really wanted to. Decreasing the process size has the advantage of making a smaller die, reducing the operating voltage, and allowing for higher overall clock speeds since electrons have less distance to travel. Downsides include increased current leakage (prescott in particular) and increased difficulty in making the new cores.

It all ends up being a balance...we can go much smaller in research than is actually used in real industry. Here at RIT we've made 31nm gates before, but it will be a long time before a process that small can actually be used in industry.

 

[mwarps]

The micron Sizing specification or "process type" means the length in nanometers or microns of the DRAM Half-pitch width.

The smaller the length, the closer things are together. Voltages drop, power consumption for similar circuits drops, power density increases, leakage increases, transistor speed increases.

Who are you? I'm also an RIT microE.

 

[umbra]

thread highjacking is rit a nice school as I'm considering going there but from what I've heard the areas kinda unpleasant

 

[(cf)Eclipse]

i go to RIT too. it's not in the city, but about 10 miles outside.. i love it

Eva and mwarps.. maybe you can answer a question for me. how come the transition from 180nm to 130nm offered a much larger voltage drop (relative drop of course) than 130nm to 90nm did, even though 130->90 is a bigger decrease in transistor size?
(btw - mechanical engineer here )

 

[mwarps]

i go to RIT too. it's not in the city, but about 10 miles outside.. i love it

Eva and mwarps.. maybe you can answer a question for me. how come the transition from 180nm to 130nm offered a much larger voltage drop (relative drop of course) than 130nm to 90nm did, even though 130->90 is a bigger decrease in transistor size?
(btw - mechanical engineer here )

Voltage drops from .18 to .13 being as large as they were was due to the relative lack of leakage. The smaller we get, the leakage increases (I think) exponentially, so we have to compensate with either voltage or doping, or some other mechanism (gate dielectrics, soi, ssoi, tisoi)

The area is only unpleasant in that it snows from October to June. Other than that, it's lovely, the food's good, there's a beer bar less than a mile away with 200+ on tap, and it's got some nice sight seeing. It's also ideal if you're gay (I'm not) as there are like two women, and they're both taken.

 

[SpoogeMonkey]

there are like two women, and they're both taken.

I heard they're dating each other......

The ssoi process is helping alot, as this 90nm process is resulting in lower vcores, lower TDP (less heat generated)..therefore cooler running cpus, and greater oc's.

 

[(cf)Eclipse]

It's also ideal if you're gay (I'm not) as there are like two women, and they're both taken.

depends on the classes.. i know the whole engineering dept is like that, but i've been in a few classes that are pretty evenly split, like writing & lit.. ugh

that explaination makes sense though, but it means we're gonna have a lot to worry about with 65nm

 

[mikelz85]

duh, why do you think you can't go one or two posts about 65nm without having the word leakage come up?

Some are worried that we may hit a wall pretty soon, and won't be able to deal with the huge increases in leakage.

Also, everything I've heard says that the "65nm" or "90nm" rating on a chip is kind of BS. More of large generalization than an actual spec, as I'm pretty sure while most see 90nm, and figure this is either the width of wiring or transistors, the truth is a little different. My technical knowledge here is a little lacking, but I'm sure someone knows what I'm talking about.

 

[(cf)Eclipse]

Also, everything I've heard says that the "65nm" or "90nm" rating on a chip is kind of BS. More of large generalization than an actual spec, as I'm pretty sure while most see 90nm, and figure this is either the width of wiring or transistors, the truth is a little different. My technical knowledge here is a little lacking, but I'm sure someone knows what I'm talking about.

my understanding is that the 130nm or 90nm is the size of the entire transistor.. while there's smaller parts in that, like the gate and whatnot.

 

[mikelz85]

my understanding is that the 130nm or 90nm is the size of the entire transistor.. while there's smaller parts in that, like the gate and whatnot.

and what I've heard is that the size of the transistors is far more variable, with 90nm being more of a way to classify something far more complicated/variable in size.

 

[mwarps]

The size of the transistor depends entirely on the application. Different Sized devices have different A/G's (oops, sorry. gains / transconductances).

The gate length of most "small" transistors at the 90nm node is only like 37nm.
That's fuckin small.

Again, the 90nm only refers to the DRAM half-pitch run on this process.

 

[(cf)Eclipse]

DRAM half-pitch

can you explain what that is?

 

[FreiDOg]

can you explain what that is?

the spacing between DRAM cells.


DRAM can be looked at as large lattice, comprised of wordlines and bitlines for accessing the individual bits. Each bit being a single transistor and a capacitor that stores the value. The wordline connects to the gate of the transistor and turns it on or off, the bitline connects to the drain and the transistor gets the charge to swing the bitline voltage from the capacitor.

That structure is a functional DRAM cell, the size of that cell, essentialy the space between adjacent bit or word lines, is the DRAM half pitch.

 

[Eva_Unit_0]

^ yeah the key idea here is that DRAM has evenly spaced lines and spaces (unlike non-DRAM devices, which are not as nicely proportioned). Pitch = width of a line and a space, but since DRAM has equal width lines and spaces, we can just use the half-pitch as a measurement of size.

And yes, I agree with mwarps about the voltage issue. Gate leakage increases exponenially as process size decreases, and the "magic number," as intel found, is down around the 90nm mark. At and beyond that, things become very difficult to deal with.

I didn't know we had so many RIT-ites here...that's pretty sweet. I'm a 2nd year microe.

 

[Scali]

Thing is, before 90 nm, nobody knew that the leakage would increase exponentially. Intel boldly went where no man has gone before, quite literally.
Now that the problem is known, solutions are being developed.
The 65 nm process is already much more efficient, and the 45 nm process is rumoured to have pretty much solved the leakage problem altogether: http://www.theinquirer.net/?article=25512

 

[(cf)Eclipse]

Thing is, before 90 nm, nobody knew that the leakage would increase exponentially. Intel boldly went where no man has gone before, quite literally.

did they not know? as eva has pointed out, smaller process sizes than are being used in cpu production certainly do exist. i'm sure tests have shown that leakage would be an issue long ago, not just because of the prescott (who's issue was architecture, not process, as is proved by dothan )

btw eva, i'm 2nd year too

 

[Scali]

did they not know? as eva has pointed out, smaller process sizes than are being used in cpu production certainly do exist. i'm sure tests have shown that leakage would be an issue long ago, not just because of the prescott (who's issue was architecture, not process, as is proved by dothan )

Intel was the first. Obviously they knew well before Prescott was on the market. But it's not easy to do something about it. They still had to continue with the Prescott. They couldn't just stop developing their CPUs and stick to the old Northwoods until the leakage problems were solved.
Same as they already have working 65 and even 45 nm samples now, but not yet on the market.

 

[mwarps]

Thing is, before 90 nm, nobody knew that the leakage would increase exponentially. Intel boldly went where no man has gone before, quite literally.
Now that the problem is known, solutions are being developed.
The 65 nm process is already much more efficient, and the 45 nm process is rumoured to have pretty much solved the leakage problem altogether: http://www.theinquirer.net/?article=25512

Saying that Intel "boldly went where no man has gone before" is a nebulous statement unless it is qualified, and used here, it is far from accurate. Several academic papers have been published in the past several years with transistors as small as .006 µm showing massive amounts of leakage. Also, mathematical models have existed for many years showing the high leakage currents, growing exponentially with the smaller devices. The problem has been known for quite a while. Solutions and workarounds to the problem are new.

i'm sure tests have shown that leakage would be an issue long ago, not just because of the prescott (who's issue was architecture, not process, as is proved by dothan )

The processes to make Dothan and the PressHot are very different. Processes are tailored to the designs that run on them for large companies like Intel or AMD. If I recall correctly, the gate dielectrics are different for these two processes, which entirely changes the rest of the processing from gate stack formation to backend/metal. If I recall, there are also fewer metal layers on the Dothans/Yonahs than on the P4s.

 

[Scali]

Saying that Intel "boldly went where no man has gone before" is a nebulous statement unless it is qualified, and used here, it is far from accurate. Several academic papers have been published in the past several years with transistors as small as .006 µm showing massive amounts of leakage. Also, mathematical models have existed for many years showing the high leakage currents, growing exponentially with the smaller devices. The problem has been known for quite a while. Solutions and workarounds to the problem are new.

Oh please... Intel was the first to actually build CHIPS at 90 nm, and on a large scale.
So the first to actually have a realistic practical test.
Please try to hide your anti-Intel bias for a moment and face the truth. Trolls like you make me sick. You think the people here don't know these things? What kind of idiots do you take us for?

 

[visaris]

As I have been told a hundred times, the Intel forum is down the hall, on the right.

 

[(cf)Eclipse]

Oh please... Intel was the first to actually build CHIPS at 90 nm, and on a large scale.
So the first to actually have a realistic practical test.

you don't need a lot of transistors to do testing for leakage. you of all people should know this

 

[ElaborateDream]

I almost feel bad that I'm an RIT Applied Networking & Systems Admin major. Drop me a PM, we'll do drinks, or lunch, and generally bitch about RIT.

 

[(cf)Eclipse]

I almost feel bad that I'm an RIT Applied Networking & Systems Admin major. Drop me a PM, we'll do drinks, or lunch, and generally bitch about RIT.

i dislike the new dining commons. there's no milk!!!

 

[Eva_Unit_0]

i dislike the new dining commons. there's no milk!!!

OMG tell me about it! The new commons sucks...there's not as much stuff, the food is cold, and the lines seem worse. I've stopped going there. But yeah...I never realized there were so many rit folk here! We should definitely do lunch sometime. (ritz, anyone?) eclipse or elaboratedream or any other rit-ers, drop me a PM or an IM if you're interested.

Anyway, to contribute something productive, I agree that the "intel did it first" idea is quite a bit of bs. As has been stated before, you don't need a full public-ready chip to learn the characteristics of a particular process. Remember that R&D stuff is always far ahead of manufacturing stages...YEARS before intel ever did manufacturing-level 90nm chips, people were already doing it routinely in lab settings. Like I said earlier, we can routinely do ~31nm features in our cleanroom, and it will take at least two more years before even 45nm chips are in industry on a retail level.

Furthermore, this is all a moot point: The heat issues with prescott are not entirely the 90nm process's fault. It is mostly the architecture's fault. Netburst was a great architectrue, but it is just too ineffecient to keep scaling. And intel found that out the hard way, through firsthand experience.

 

[ChingChang]

I go to RIT too... had no idea some of you are students here.

 

[Scali]

you don't need a lot of transistors to do testing for leakage. you of all people should know this

Erm, you don't test for leakage in a yes/no fashion. All transistors have leakage. The question is more about how much leakage, and where that leakage goes. Just having one transistor under laboratory conditions is no indication of what will happen in an actual chip, where lots of transistors are positioned side-by-side, and layer upon layer.
And ofcourse you also have to assume realistic circumstances. In a lab it may be possible to build a single transistor that has virtually no leakage, but if it is not possible to use that technology in actual mass-produced chips, or at reasonable cost, there's no point, is there?
Fact remains that Intel was the first to mass-produce 90 nm chips, so they were the first to run into the practical problems (and they may also have been the first to have done tests in the lab, but they never document those things. Obviously Intel researches new technologies at smaller scales before they design their actual chips and go into mass-production).

 

[Scali]

As I have been told a hundred times, the Intel forum is down the hall, on the right.

An AMD-forum is no excuse to practice revisionist history or distort the truth to make AMD look better.
So spare me your excuses.
And as I said a million times before, I actually own and use an AMD processor daily.
So I have just as much right as you to post in the AMD forum, if not more.

 

[Eva_Unit_0]

scali I see what you're saying, but I think you're missing my point--yes, prescott was the first 90nm chip, but I believe it had much more playing against it...namely netburst. I mean, heat and power characteristics of prescott are DRASTICALLY different from those of AMD's first 90nm attempt (winnie), as well as intel's own Dothan. The fact that intel pulled off dothan so beautifully (and in such close time proximity to prescott) makes me suspect that prescott's issues were not due entirely to the immature 90nm process, but more to netburst's ineffecient architecture. And plus, even as intel has really matured their 90nm process a lot (prescott 6xx and smithfield) the heat dissipation has not decreased tremendously, again showing that their "guinea pig" status at first was rather meaningless.

 

[(cf)Eclipse]

An AMD-forum is no excuse to practice revisionist history or distort the truth to make AMD look better.

where in here are we trying to imply that amd is better? i was simply trying to say that you don't need an entire chip to predict how things will work out. sure, it helps accuracy, but if i know anything, it's possible to make a reasonably accurate guess from a small sample, and here you come in saying that intel did it first.

 

[Scali]

scali I see what you're saying, but I think you're missing my point--yes, prescott was the first 90nm chip, but I believe it had much more playing against it...namely netburst.

Yes, but I covered that many times before in other threads.
AMD is just lucky to be in an underdog position. First of all they were much later with 90 nm than Intel. By this time Intel had also decreased the temperatures, but that didn't stop people from still using the data from the first processors, and ignoring the new and improved steppings.
Secondly, AMD didn't cut down power consumption a lot either with their 90 nm, and their clockspeeds were hard-limited at 2.6 GHz for ages, which they also were at 130 nm. Only now do we see the first 2.8 GHz models. But for AMD this was not such a big deal, since their CPUs already ran cooler, and their CPUs were already faster.

 

[mikelz85]

unless Intel is making/designed all their own tools and manufacturing equipment used in the 90nm process, I highly doubt they were the first ones to attempt it. Of course, it is entirely possible that the equipment manufacturer just sold them stuff for Intels fab and said "have fun seeing if it works", but I doubt a full production microprocessor would be the first project to delve into 90nm, testing on a smaller scale would be done first, or else it could cost you a shitload of money running blind.

Wouldn't it make sense that even in order to calibrate the equipment for 90nm use, you'd do some 90nm work with it? Now I'm not exactly an expert by any means, but I am aware that Intel and AMD are far from flying solo when it comes to the manufacturing process.

I'm willing to bet that leakage is tested on a small scale at first, (maybe one or two transistors), then more, then more, until they are reasonably sure it can support an architecture. Of course, the could just skip from 1 transistor in a lab to fully stocked wafers, but I really don't think that'd be prudent business, engineering, or science.

 

[Scali]

where in here are we trying to imply that amd is better? i was simply trying to say that you don't need an entire chip to predict how things will work out. sure, it helps accuracy, but if i know anything, it's possible to make a reasonably accurate guess from a small sample, and here you come in saying that intel did it first.

Oh please, grow up.

 

[(cf)Eclipse]

Secondly, AMD didn't cut down power consumption a lot either with their 90 nm

89w to 67w isn't a decent drop? i guess i'll stop here since i'm getting too involved in this now. i'll let the guys who actually know their stuff battle it out

 

[mikelz85]

Wait, you say the reason AMD chips were so sucessful on 90nm is because they had all of Intels early mistakes to learn from? Is there any documentation that AMD had access to all of Intels intellectual property? Does this stuff fall under their "shared" agreement? Somehow I think Intel would prefer to keep AMD in the dark, but if you've got documentation proving AMD had inside Intel 90nm info, and that's partly why AMD put out a quality product, I'd love to see it. I just can't imagine unless Intel was legally obligated to share that info (and even then...) that they'd disclose anything of use to AMD.

 

[Scali]

Wait, you say the reason AMD chips were so sucessful on 90nm is because they had all of Intels early mistakes to learn from? Is there any documentation that AMD had access to all of Intels intellectual property? Does this stuff fall under their "shared" agreement? Somehow I think Intel would prefer to keep AMD in the dark, but if you've got documentation proving AMD had inside Intel 90nm info, and that's partly why AMD put out a quality product, I'd love to see it. I just can't imagine unless Intel was legally obligated to share that info (and even then...) that they'd disclose anything of use to AMD.

You take things too literally.
Obviously Intel never officially disclosed anything to AMD.
But a lot of info has leaked out into the press, and who knows how much info leaked out to AMD. And I'm sure AMD got its hands on some of Intels Engineering Samples, and examined them closely.
Obviously AMD isn't going to tell anyone exactly how much they know about Intel either.
And actually it's more IBM than AMD anyway.
But do you really think that it's coincidence eg that Intel develops Strained Silicon, and IBM/AMD come up with their own version only a few months later?