Tualatin latency

[commodore]

got a question. if the L2 cache latency of the Tualatin celeron is offically 1...then how come mine is 2 (i checked another chip and it shows 1). did i get cheated or sometin...???

the chip is a 1.1@1.53GHz , 1.57 Vcore, aircooled.

 

[Josh_B]

I could be wrong, but wasn't the cache of the Tualatin Celerons actually 2, while the PIII-S' were the Tualatins with an L2 latency of 1?

 

[pxc]

Try it with CPU-Z: http://www.cpuid.com/

The Tualatin P3 reports a "0" latency and the Tualatin Celeron reports a "1" latency.

If you do get a 2 cycle latency in CPU-Z, that's pretty strange news. It may just be that the program you're using is correcting the impossibility of the Tualatin P3 having a 0 cycle latency by showing the Tualatin P3 as 1 cycle and the Tualatin Celeron as 2 cycles.

The Coppermine P3 shows 0 cycle latency and the Coppermine Celeron shows 1 cycle latency.

 

[SLee]

The L2 caches of all P3s were never that fast, typically they were 7 cycles. Use cpu-z's cache latency benchmark found in its About section.

 

[pxc]

n/m

 

[commodore]

2 cache levels detected
Level 1 size = 16KB latency = 3 cycles
Level 2 size = 256KB latency = 8 cycles (5 cycles for this only level)


I got this with the CPU-Z cache bench...also WCPUID also gives L2 latency as 2...why??

 

[SLee]

Originally posted by commodore
2 cache levels detected
Level 1 size = 16KB latency = 3 cycles
Level 2 size = 256KB latency = 8 cycles (5 cycles for this only level)


I got this with the CPU-Z cache bench...also WCPUID also gives L2 latency as 2...why??

Those latency values are correct for a P3 Tualatin. As to why WCPUID says its 2, who knows?