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“Often, multiple factors build on top of each other. “One of the ways that we address safety is things like triple voting flops,” says Graham. “If you triple the number of flops, you are driving gate count higher, and that is part of complexity. It is also driving the need for things like 3D-IC and chiplets. These require a broad array of experts. It’s no longer just a digital designer. We need a digital and analog designer, a digital verification engineer. Now you need a safety verification engineer or a safety designer. And then the system-level expert. You need all of your teams to have some expertise in this, and you need these vertical experts, which is driving up the requirement for more talent. You’re either taking a good verification, or good design engineer, good place-and-route person, and saying you’re going to be our expert in this vertical. Now you need to replace that person. Or you need to bring that in, and suddenly your team is that much larger.”
Functional verification has become totally wrapped into the entire development flow. “Power is a good example,” says Salz. “You need to be able to estimate power early on, and make sure, at the system level, that you’re staying within that envelope. Some things are going to get worse. Thermal is a big thing with multi-dies. You need to start thinking about all of these things. You need to think about how you are going to test it once you’ve integrated the chiplets. Are you going to test as you integrate, or are you going to just build the entire SoC and then test it?”
Some point tools may not yet be ideally integrated into flows. “Thermal is a new consideration, but many of the tools available use a brute-force dumb approach of doing synthesis to get everything to gates, just to figure out the power,” says Swinnen. “Synthesis takes a long time, a lot of resources, and is very capacity-limited. A better approach is to use heuristics that are based on many years of experience. These look at the circuit and divide it into different function types. This is random logic, this is memory access, this is clock logic, this is data path logic, and apply different heuristics to each of these regions. It builds up an estimate of the power in the system. It is often within 5% of the final gate level numbers. The point of this is optimization. ‘I’ve got this architecture. What if I change it? Would that increase the power or lower the power?’ You’re not worried about the last watt. You’re worried about if your optimization is increasing or decreasing the power. It is also the time in the process where power and thermal are being understood, and which cycles need to be identified for use in other parts of the flow.”
Conclusion
There is an increasing amount of newness in many designs today. This is driven by technological advancements, domain requirements, and changing views of the system and the methodologies required to design them. It often requires the influx of new expertise that can be difficult to properly integrate. The need for larger, more diverse teams is hampered by an industry-wide lack of talent, and this is causing significant instability within companies. The fact that there is a dip in first-time success rates is perhaps unsurprising, but the real question is whether this is the beginning of a longer decline, or if this is a wakeup call for change.”
Source: https://semiengineering.com/trouble-ahead-for-ic-verification/
Functional verification has become totally wrapped into the entire development flow. “Power is a good example,” says Salz. “You need to be able to estimate power early on, and make sure, at the system level, that you’re staying within that envelope. Some things are going to get worse. Thermal is a big thing with multi-dies. You need to start thinking about all of these things. You need to think about how you are going to test it once you’ve integrated the chiplets. Are you going to test as you integrate, or are you going to just build the entire SoC and then test it?”
Some point tools may not yet be ideally integrated into flows. “Thermal is a new consideration, but many of the tools available use a brute-force dumb approach of doing synthesis to get everything to gates, just to figure out the power,” says Swinnen. “Synthesis takes a long time, a lot of resources, and is very capacity-limited. A better approach is to use heuristics that are based on many years of experience. These look at the circuit and divide it into different function types. This is random logic, this is memory access, this is clock logic, this is data path logic, and apply different heuristics to each of these regions. It builds up an estimate of the power in the system. It is often within 5% of the final gate level numbers. The point of this is optimization. ‘I’ve got this architecture. What if I change it? Would that increase the power or lower the power?’ You’re not worried about the last watt. You’re worried about if your optimization is increasing or decreasing the power. It is also the time in the process where power and thermal are being understood, and which cycles need to be identified for use in other parts of the flow.”
Conclusion
There is an increasing amount of newness in many designs today. This is driven by technological advancements, domain requirements, and changing views of the system and the methodologies required to design them. It often requires the influx of new expertise that can be difficult to properly integrate. The need for larger, more diverse teams is hampered by an industry-wide lack of talent, and this is causing significant instability within companies. The fact that there is a dip in first-time success rates is perhaps unsurprising, but the real question is whether this is the beginning of a longer decline, or if this is a wakeup call for change.”
Source: https://semiengineering.com/trouble-ahead-for-ic-verification/
