Transistors Will Stop Shrinking In 2021

Megalith

Megalith

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That is what the latest semiconductor roadmap predicts, anyway. Shrinking transistors in microprocessors is no longer “economically desirable” and manufacturers will try engineering vertically instead, stacking circuitry.

For some, this change will likely be interpreted as another death knell for Moore’s Law, the repeated doubling of transistor densities that has given us the extraordinarily capable computers we have today. Compounding the drama is the fact that this is the last ITRS roadmap, the end to a more-than-20-year-old coordinated planning effort that began in the United States and was then expanded to include the rest of the world.
 
Just a heads up in case you see this before the PM I sent.

The comments link on the front page is broken.

Edit: And now it is working.
 
westrock2000 said:
wonder if they will come up with crazy nano heat tubes between the silicon substrates to extract out the heat of stacking.
Click to expand...

It's really hard to predict some things these days 5 years out, give it a little more time there will probably be a lot of nano tech self improving things.
 
As someone who has worked in nanoscience in academia and the semiconductor industry, I'm not convinced we will see anything crazy like CNT to transfer heat. There are numerous challenges to growth, and homogeneity in particular.


It's certainly not impossible, but it's hard to see it being practical.
 
They will have to do something with the heat though. You can't just add more transistors (and leakage) into the same surface area and not pay any consequence. And putting metal spreaders in between the silicon will add thickness. And even then, what do you do with the heat once you get it to the edge? This is what makes it fun to watch, and I'm sure they will come up with novel solutions to the problems.
 
I don't exactly agree with the article...

"The doubling of transistor densities hasn’t been linked to improvements in computing performance for some time, notes Tom Conte, the 2015 president of the IEEE Computer Society"
 
"economically desirable"

Sounds like a god damn Oil Company phrase.
 
They have said this before.. I'm pretty sure it's been posted on HardOCP that getting smaller just wasn't going to happen? It's been said many times and yet the shrink still comes. Mostly it's moore's law that people keep saying can't stay... yet it has.

Octo-core and beyond will be the normal soon. Heck it already is on our phones.
 
As much as this sort of thing has been said for years, we ARE reaching a point where the transistor wall size is getting awfully close to the size where an electron's probability field can reliably tunnel an electron reaction WAY outside of where it needs to be and interfere with other parts of the chip.

The big issue here is that once you get right on that threshold, where do you go? We all know architecture can improve and efficiency can be attained without shrinking the size of the transistor, but after a few decades of that, you would think we would reach peak architecture efficiency. What is needed is a new form of semiconductor that can operate faster...

Enter Organic structures such as graphene or CNTFETS.
 
chenw said:
Tactical Fusion Cubes,
Click to expand...

The next logical step is Neural net processors; Learning Computers.

latest
 
Grimlaking said:
They have said this before.. I'm pretty sure it's been posted on HardOCP that getting smaller just wasn't going to happen? It's been said many times and yet the shrink still comes. Mostly it's moore's law that people keep saying can't stay... yet it has.

Octo-core and beyond will be the normal soon. Heck it already is on our phones.
Click to expand...

There are true physical limits that cannot be overcome... unless you also know of a way to shrink the size of electrons and atoms.

We're already running into issues with leakage at current process node sizes resulting in not enough insulation between gates. It's not the size of the conductor but the amount of space between them. It's specifically a problem with Skylake mobile processors, where running an OS that does not support lower power states can cause the CPU to fail prematurely.

While, yes, the theoretical maximum has been lowered each time, it was not due to atomic limits previously... but ability to manufacture at those sizes.

This time, it really is coming down to atomic limits. The current theoretical PRACTICAL limit to process size is 6nm before you start running into serious problems with failure. So the jumps to 7nm and 5nm will be especially interesting to watch to see if and how they get around issues. We're at 14nm with Skylake and have already have had some problems. 10nm is next with Cannonlake and we'll see how that goes. 10nm already requires a whole new process with different materials.

Suppose everything goes perfectly well, then 1nm could be our atomic limit. Money's at 6nm, though.
 
We can already see a lot of companies falling of below 28nm because it cant repay itself ever. Some companies do 14/16nm today, while they will only lose money on it as well. EUV will some parts of this, but volume is the key. So its not a surprise. The endgame seems to be between TSMC and Intel on the foundry front. For clients, I guess Intel vs Apple.
 
Thanks. All my thinking is now to the voice of mr Schwarzenegger.

Get bier. Come with me if you wanna shit.etc.
 
I thought integrated circuits already stacked connections vertically. It will be great if they could just get two chips worth of potential in the same footprint without the extra socket. Stacking chips is the way of the future.
 
I don't doubt people much smarter and more highly qualified than me have already thought of this, but I wonder if 'crinkle cut' wafers could offer a solution here? Introduce microscopic ridges and valleys to increase the surface area without increasing the footprint (or more importantly messing up clock domains).

Perhaps some sort of inert fluid medium could be introduced into those valleys to carry heat to an integrated heat spreader too, even if you then stacked them in 3D (provided the layers were properly aligned).

I realise that even producing such wafers would be incredibly difficult, never mind the challenges of actually etching the things, but humanity never let something being difficult stop technological process before.
 
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