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sandra cpu test

C

chuckm1020

[H]ard|Gawd
Joined
Jun 12, 2003
Messages
1,175
Does this score seem right for a 3.4EE LGA775? Are the MIPS suppost to be a little lower than a 3.6ghz 560 LGA775?
4176be56175ff.jpg
 
I just hit 11868 with my computer.. (first one in sig)
 
Just for a reference, I just tested my northy (3.2 @ 3.52) @ 10685 with UD running in the background.
 
does my score sounds right for a 3.4ee at stock speeds? does the extra l3 cache not really make a difference on the sandra test?
 
my scores, 2.4c@3.42

10412 MIPS
7582 MFLOPS

post your multimedia cpu benchmark results, lets see what those are like
 
The one thing I noticed is that the "MIPS" lower than the "MFLOPS" on the graph. I looked through Sandra and on most procs the graph for the "MIPS" goes further to the right in relation to the "MFLOPS". What that means exactly, I have no idea. But it might show a problem somewhere. Good Luck.
 
Maybe it's just me but it's possible you're looking at the graph a bit scewed. The MIPS is about where it should be (compare the the other P4 550 3.4E) but your MFLOPS/SSE2 performance is higher than it should be, matching a CPU clocked 200Mhz faster. So no, I don't think there's anything wrong with your setup. SiSoft updates their benchmark programs often but sometimes not the reference CPU/boards/etc. Possible reason why your scores look a bit strange.
 
yah, that does make sense, because it as at 3.4ghz so the MIPS are right for the clock speed.... also here are the cpu-multimedia bechmarks requested..
417d50cacc0ec.jpg
 
MIPS = Million of Instructions Per Second. This is directly related to frequency, so the cache will have no affect on this score.

Theoretically a Celeron at a higher MHZ could outscore an EE at a lower MHZ in this test. (if the instructions tested are small enough to fit in the celeron's cache)

==>lazn
 
Lazn_Work said:
MIPS = Million of Instructions Per Second. This is directly related to frequency, so the cache will have no affect on this score.

Theoretically a Celeron at a higher MHZ could outscore an EE at a lower MHZ in this test. (if the instructions tested are small enough to fit in the celeron's cache)

==>lazn
Click to expand...
ah :D yes this does make more sense, thats what i started thinking to, maybe with the MIPS cache has nothing to do with and only the clock speed. what is the multi-media benchmark testing. i seemed to do really well on that test. i kicked the 3.6ghz ass :D LOL
 
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