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Reverse Hyperthreading?

I see. thanks. so what is the explanation for the drastic increase in performance on that german website?
 
I looked up "reverse hyper-threading". That's bunk. At best, resources unused by low activity threads are simply available to active threads, which is the way it is already, as much as feasible. Latency would go through the roof shuffling data to another core for a single thread. You'd have to design a single core that embodied a dual core that each embodied two threads.
 
numbercruncher said:
http://www.heise.de/newsticker/meldung/Skylake-mit-inversem-Hyper-Threading-2779793.html

Thanks anyways
Click to expand...
The same author made a newer post from IDF and dismisses his earlier theory: http://www.heise.de/newsticker/meld...in-wenig-die-Skylake-Architektur-2784862.html

There is no inverse hyperthreading in Skylake and he thinks the score in that one test improved drastically from large improvements in the caches (L1/L2 bandwidth doubled, L2/L3 fabric improved), prefetch, TLB and higher DDR4 memory bandwidth. In the other thread I also suggested compiler improvements which benefit Skylake could also be responsible for some of the gain.
 
zaniix said:
I heard a rumor that the AMD Nano is reverse hyper threading compatible
Click to expand...

Oh hell, then AMD has reverse hyperthreading first!

Because they had to invent a time machine and go back in the past to steal reverse hyperthreading from the Nazis before it was destroyed by the Russian spies!

And then they will use their time machine to release Zen with reverse hyperthreading before Bulldozer's release, causing a wormhole in the fabric of space-time.

You heard it here first! AMD's Zen has Nanotech time travel and reverse hyperthreading! Also compatible with AMD Nano with reverse hyperthreading (TM) compatible
 
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xorbe said:
I looked up "reverse hyper-threading". That's bunk. At best, resources unused by low activity threads are simply available to active threads, which is the way it is already, as much as feasible. Latency would go through the roof shuffling data to another core for a single thread. You'd have to design a single core that embodied a dual core that each embodied two threads.
Click to expand...
That sounds a lot like what people were incorrectly calling AMD's CMT before Bulldozer was released.
 
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