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IEEE Spectrum reports that Rakesh Kumar and his associates are working on a "wafer-scale" interconnect for GPUs. Instead of fabricating multiple GPUs on a massive silicon wafer, or using power hungry and slow traditional interconnects like existing supercomputers use, Kumar wants to use a "silicon interconnect fabric" as a replacement for a circuit board. In other words, Kumar wants an interconnect that would (theoretically) allow 40 GPUs to be seen as "one giant GPU" from the perspective of programmers. Simulations of a 41 GPU design showed that it significantly sped up computation while consuming less energy than 40 GPUs with a conventional interconnect, and he says "the team has started work on building a wafer-scale prototype processor system, but he would not give further details." Kumar will present more information on his progress at the IEEE International Symposium on High-Performance Computer Architecture later this month.
SiIF replaces the circuit board with silicon, so there is no mechanical mismatch between the chip and the board and therefore no need for a chip package.The SiIF wafer is patterned with one or more layers of 2-micrometer-wide copper interconnects spaced as little as 4 micrometers apart. That's comparable to the top level of interconnects on a chip. In the spots where the GPUs are meant to plug in, the silicon wafer is patterned with short copper pillars spaced about 5 micrometers apart. The GPU is aligned above these, pressed down, and heated. This well-established process, called thermal compression bonding, causes the copper pillars to fuse to the GPU’s copper interconnects. The combination of narrow interconnects and tight spacing means you can squeeze at least 25 times more inputs and outputs on a chip, according to the Illinois and UCLA researchers.
SiIF replaces the circuit board with silicon, so there is no mechanical mismatch between the chip and the board and therefore no need for a chip package.The SiIF wafer is patterned with one or more layers of 2-micrometer-wide copper interconnects spaced as little as 4 micrometers apart. That's comparable to the top level of interconnects on a chip. In the spots where the GPUs are meant to plug in, the silicon wafer is patterned with short copper pillars spaced about 5 micrometers apart. The GPU is aligned above these, pressed down, and heated. This well-established process, called thermal compression bonding, causes the copper pillars to fuse to the GPU’s copper interconnects. The combination of narrow interconnects and tight spacing means you can squeeze at least 25 times more inputs and outputs on a chip, according to the Illinois and UCLA researchers.
