"Real" quad core.. when?

[CyberDeus-RagDoll]

I have to explain what I mean by real quad core.

For example. My E6700 (dual core, obviously) is 2 cores, using 1 cache.
My QX6700 (quad core) is basically, 2 E6700s in one package. the e6700 isn't "4 unified cores" but doubled up, dual unified cores.

When will there be (in LGA775) a true, unified quad core solution? Do we have code names, road maps, etc to show this info?

Alternately, is amd's "4x4" 'real' quad core, or is it a similair solution to the qx6700 (and qx6600)

 

[theriverlethe]

I have to explain what I mean by real quad core.

For example. My E6700 (dual core, obviously) is 2 cores, using 1 cache.
My QX6700 (quad core) is basically, 2 E6700s in one package. the e6700 isn't "4 unified cores" but doubled up, dual unified cores.

When will there be (in LGA775) a true, unified quad core solution? Do we have code names, road maps, etc to show this info?

Alternately, is amd's "4x4" 'real' quad core, or is it a similair solution to the qx6700 (and qx6600)

What is the supposed advantage of "real" quad core?
I believe 4x4 will be two "real' quad cores (two sockets), when AMD finally releases a quad core processor. (Q3 2007?) Currently, you can only get two dual-cores for a 4x4 motherboard, and Intel's quad-core performance is equal or better, with much lower power consumption (and still at lower clock frequencies).
I believe the rumor is that Intel will have a 45nm "true" quad core at 4Ghz, some time in '08. AMD should have their new architecture out mid to late next year, so it will be interesting to see who is on top at that time, and whether Intel reclaims the lead in '08 (assuming they lose it).

 

[InorganicMatter]

There is no such thing as "real" or "native" quad core. There is only "real" world performance.

Kenstfield has "real" performance.
4x4 does not have "real" performance.
And I'm willing to be K8L doesn't have "real" performance either, since AMD would have announced it to the world by now given their arrogant track record.

What is the supposed advantage of "real" quad core?

THERE IS NONE! Say it with me: T-H-E-R-E_I-S_N-O-N-E!!!!!! All that matters is real performance. If I had the choice between a "native" quad-core with shared cache, and four single cores stuck together with Elmer's Glue, I'd whatever one performs better, connecting method be damned!

 

[chrisf6969]

there's not really a disadvantage of non-native quad.

I believe when Intel launchs its native ("real") quad core at 45nm its going to have 12Mb of unified (shared) L2 cache!!! That would REALLY kick ass in some apps that need a lot of cache! Imagine if its a single threaded app, it could have nearly all 12Mb to itself (gaming!)

AMD's 4x4 is not native either. And its a HUGE power HOG, and Intel is still faster even though AMD has a better "FSB" (multiple Hypertransport buses, Integrated memory controller, etc)

When AMD comes out with native quad its going to have 4 cores each with 512Kb of L2, then a shared L3 cache.

 

[savantu]

A thing is n-core as long as it uses one socket , that is 1P/1S

QX6700 is quad-core.

4x4 is a 2P/2S solution which exist since the '60s.

Bragging which is real and which is not is the poor man's defense when he has nothing.I couldn't care less if I had a bunch of midgets with handheld calculators inside my CPU as long as it works.

 

[Mabrito]

I couldn't care less if I had a bunch of midgets with handheld calculators inside my CPU as long as it works.

QFT

People are really starting to irratate me with this native quad core crap. I dont care if its native or not, if it works and works good at a price I can afford then im going to get it. Ill take the midgets if its better than its competitor!!!!

 

[wee96]

If a processor with two pieces of silicon containing two cores each outperforms a processor with four cores on one piece of silicon, sorry but I want the two pieces. Its complete hype that AMD is creating since they really have nothing they can say about the core technology, it is some serious power and kentsfield is an awesome cpu. Others have stated my opinion also, I could care less if its one or two or three pieces of silicon, I care about the performance.

 

[InorganicMatter]

Bragging which is real and which is not is the poor man's defense when he has nothing.

Kind of like AMD?

 

[Klintus Fang]

I agree with all the people that say there's no advantage. There is in fact more potential problems if all 4 of those cores in the package where sharing a single unified cache for example, because that would be 4 cores sharing a single cache's BW. If all else was equal I'd prefer two separate caches, with 2 cores sharing each one. Not to say that so-called "native quads" won't happen, but it's likely going to require a significant redesign of that last level cache to work well.

the things that matter if you have 4 cores in a single package is whether or not you've got enough pins leading out of the package to provide the memory bw that those 4 cores will demand, whether or not the amount of cache available to each core is going to help keep the memory bw demands of each core from being too high, whether or not you have enough cache bw to feed the cores when the cache activity is high, and whether or not you can keep the temperatures down while all 4 cores are running and still get good performance out of each one.

whether or not they are on the same die and whether or not they all share the same internal cache is really not relevant, and as I mentioned, for the end user there is only increased risk with having all 4 cores sharing the same cache unless the designer of said cache can assure you the cache has enough bw to feed all four cores without taking a latency hit.

 

[bob]

Anyone here take a look at Sun Microsystems 8-core CPU that has been out for about two years?

http://en.wikipedia.org/wiki/UltraSPARC_T1
"UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. The processor is available with four, six or eight CPU cores, each core able to handle four threads concurrently. Thus the processor is capable of processing up to 32 threads concurrently." "Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1.2 GHz."

http://en.wikipedia.org/wiki/UltraSPARC_T2
The T2 is a derivative of the UltraSPARC series of microprocessors. The processor, manufactured in 65 nm, is available with eight CPU cores, and each core is able to handle eight threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads.

The T1 supposedly is comparable to 4 Intel dual-core Xeon 3.0's, but only draws 72 watts.

Now yes, This T1 is far different from a conroe (or any other desktop cpu), but im just trying to make a point... if a company with as pricy of parts as SUN has decided its a good idea to cram 8 cores on one chip, it cant be too bad of an idea. Im all for multiple cores on one chip (Mini-itx quad core anyone? ). Less power, less cost, less space occupied.

 

[Klintus Fang]

it's not a bad idea in general, but the point is there isn't necessarily any benefit to having them on the same chip as oppossed to having them on separate dies, especially for a desktop. sure, one could design a desktop CPU that has 4 cores on 1 die, but the fact that it is designed that way doesn't make it any better than one that has two dies. a lot of people seem to blindly assume that having it all on the same die is intrinsicly better, and THAT assumption is erroneous.

Sun is not a good example in this context. the single threaded performance of their cores is and always has been horrible. That is how they fit so many cores in one package, they end up accepting significant performance loss on the single threaded performance to do it. They are designing those cores for a market (i.e., the backend server that manages a giant data base and regularly runs multiple concurrent threads) where single threaded performance is irrelevant because most of the threads spend most of their time idling while they wait for memory requests to complete anyway.

 

[wee96]

Anyone here take a look at Sun Microsystems 8-core CPU that has been out for about two years?

http://en.wikipedia.org/wiki/UltraSPARC_T1
"UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. The processor is available with four, six or eight CPU cores, each core able to handle four threads concurrently. Thus the processor is capable of processing up to 32 threads concurrently." "Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1.2 GHz."

http://en.wikipedia.org/wiki/UltraSPARC_T2
The T2 is a derivative of the UltraSPARC series of microprocessors. The processor, manufactured in 65 nm, is available with eight CPU cores, and each core is able to handle eight threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads.

The T1 supposedly is comparable to 4 Intel dual-core Xeon 3.0's, but only draws 72 watts.

Now yes, This T1 is far different from a conroe (or any other desktop cpu), but im just trying to make a point... if a company with as pricy of parts as SUN has decided its a good idea to cram 8 cores on one chip, it cant be too bad of an idea. Im all for multiple cores on one chip (Mini-itx quad core anyone? ). Less power, less cost, less space occupied.

The only point made is that its more space efficient, its not any better for performance.

 

[bob]

The only point made is that its more space efficient, its not any better for performance.

uhh..

Im not quite sure why your signling me out and responding as if I had quoted you and misread it... there are 9 other posts here . Though regardless, thats about the only point I made (assuming you read my post). 8 cores on one cpu, each performing similar to a 3.0Ghz xeon core, and only drawing 72 watts...

My other point was, intel isnt the only one marketing this as a good idea.

 

[savantu]

uhh..

Im not quite sure why your signling me out and responding as if I had quoted you and misread it... there are 9 other posts here . Though regardless, thats about the only point I made (assuming you read my post). 8 cores on one cpu, each performing similar to a 3.0Ghz xeon core, and only drawing 72 watts...

My other point was, intel isnt the only one marketing this as a good idea.

Niagara is a special purpose CPU designed primarly for web serving tasks.

Xeons are multi purpose CPUs.They handle everything at acceptable speed.

Intel recently created a 80 core , 4GHz@98w CPU capable of performing 1200 GFLOPs.A woodcrest at 3GHz can perform 24GFLOPs.If Intel wants , it can.

 

[Klintus Fang]

Intel recently created a 80 core , 4GHz@98w CPU capable of performing 1200 GFLOPs.A woodcrest at 3GHz can perform 24GFLOPs.If Intel wants , it can.

I think that announcment was smoke and mirrors. Personally I think otellenni was holding up a prototype of an 80 core special purpose DSP chip design rather than a general purpose CPU. One thing for sure, when Intel made that 80 core announcement, they never claimed it was a general purpose CPU, and if it was... they would have said so.

 

[wee96]

uhh..

Im not quite sure why your signling me out and responding as if I had quoted you and misread it... there are 9 other posts here . Though regardless, thats about the only point I made (assuming you read my post). 8 cores on one cpu, each performing similar to a 3.0Ghz xeon core, and only drawing 72 watts...

My other point was, intel isnt the only one marketing this as a good idea.

Uhh... I wasnt singling you out, I was saying your example only really shows it saves space, it doesnt provide better performance and what not.

 

[bob]

Uhh... I wasnt singling you out, I was saying your example only really shows it saves space, it doesnt provide better performance and what not.

The first part of "singling me out" was some of my dry sarcasm, seems to have failed.

 

[wee96]

The first part of "singling me out" was some of my dry sarcasm, seems to have failed.

So did mine

 

[CyberDeus-RagDoll]

What's the benefit?

One of the big things that intel spouts about the superiority of the C2D platform over their OWN "P4D" is the fact that since there is a shared cache, the content of the cache doesn't have to be written twice.

a P4D @ 3.0GHZ x2mb cache doesn't have "4mb cache" it has 2mb cache, cause EVERY SINGLE damn thing gets written twice.

a QX6700 doesn't have an 8mb cache. It has 2 x 4mb caches. The content of the cache for cores 0 & 1 match the content of the cache for cores 2 & 3

Many tests show that, in some situations, the QX6700 underperforms it's dual core brother, the E6700. [most notably gaming, but multimedia in general]


If you don't understand why 4 cores working harmoniously together is superior to two teams of two, then I can't even begin to explain to you why I want to know when the product will be available.

Suns 8core design is nice, but not quite going to run the same hardware, o/s, applications as say a more mainstream product.


Yes, there is a low amount of available multithreaded apps, however, that doesn't mean they are non existent.

There is more waste in a "double dual" configuration than in a "true quad" configuration.

It may only be marginally better (whenever it is available) but, in the instances where quad core CAN be taken advantage of (think... these are the same instances where a 4 way processing solution such as that which is offered by the xeon / opteron (8xx) / itanium / etc...

a pair of dual socket computers working in tandem are not as efficient (depending on the app) as a single, 4 way processing system.

What I want to use it for is irrelevant. I want to know when it will exist, that was all.

What is the supposed advantage of "real" quad core?

You are building a simple, "one room school house" out of bricks,
You have FOUR masons working together. One mason per wall.

vs

You are building a pair of one room school houses.
2 masons per house.

Which school will be completed first? The 1 school being worked on by 4 men, or the 1 school being worked on by 2 men?

Yes, in double the time you'll have double the product, but, that still leaves the kids waiting to attend school, twice as long

I argue, that, the 4 masons working together could PROBABLY build an even BIGGER space before the two teams of two can get ONE done.




Why do I want it on a desktop solution? I don't like paying $1000 for my motherboards, then having to buy "special" ram, "Special" psus (n+1, eps) for my desktop computer.

 

[theriverlethe]

You are building a simple, "one room school house" out of bricks,
You have FOUR masons working together. One mason per wall.

vs

You are building a pair of one room school houses.
2 masons per house.

Which school will be completed first? The 1 school being worked on by 4 men, or the 1 school being worked on by 2 men?

Yes, in double the time you'll have double the product, but, that still leaves the kids waiting to attend school, twice as long

I argue, that, the 4 masons working together could PROBABLY build an even BIGGER space before the two teams of two can get ONE done.

I question your analogy.
The two teams of two would be working on one school, but they would occassionally have to negotiate through a third party to share each others' tools.
However, the two men teams charge less combined than the four man team, and can start the job a year sooner.

 

[Klintus Fang]

What's the benefit?

One of the big things that intel spouts about the superiority of the C2D platform over their OWN "P4D" is the fact that since there is a shared cache, the content of the cache doesn't have to be written twice.

a QX6700 doesn't have an 8mb cache. It has 2 x 4mb caches. The content of the cache for cores 0 & 1 match the content of the cache for cores 2 & 3

Intel couldn't have said that because that doesn't make any sense. If there are two separate caches, then the caches will not be required to contain the same data. In fact most of the time the data in each cache will be different. The cache for core 0 will contain the data core 0 is using, and the cache for core 1 will contain the data that core 1 is using. They will not both be written with the same data all the time. Only a tiny percentage of the data in each cache will be the same across the two caches. I don't know what official Intel statement you think you are quoting, but whatever it was you could not have been understanding whatever it is Intel said, because what you are saying is inconsistent with the way that caches actually work.


The rest of what you say is analogies that are built on the same errors in reasoning that you make in the beginning of your post.


Now, there are some ways in which sharing the cache has a benefit.

1. if the threads running on the cores are really operating on the same data. In that case, and in only that case, will the data have to be stored in both caches. Unfortunately, even heavily multi-threaded server applications only share a small percentage of the actual data in the caches, and desktop and gaming applications share none of the data in the caches. So for gaming, this observation is irrelevant. And even for the server market, though it is sometimes relevant, and still doesn't automatically mean that sharing the cache is magically better. Even in that space, it will vary from application to application.

2. it reduces the cache-to-cache snoop traffic. snoop traffic is when the caches have to check each others contents for the purposes of keeping the data coherent. Whether or not that is an issue depends upon how the snoop protocol has been designed and at what level the snoops are managed, and on whether or not the FSB had enough bw to cover the extra FSB traffic that might occur. Do the snoops have to hop through the memory controller or is there a layer of logic on the die that manages coherency without having to go out to the memory controller? I don't actually know how the snoop protocol works for these chips so I can't answer that question. But I suspect that there is enough FSB bandwidth to handle it in either case if there are just two links to the memory controller, and that the issue is again only relevant to multi-threaded server apps that have heavy data sharing.


What you are reasoning is probably a mis interpretation of one of the two things above. If so, you are massively overstating and mis construeing the actual issues.

 

[Ranari]

However, the two men teams charge less combined than the four man team, and can start the job a year sooner.

Rofl!

 

[CyberDeus-RagDoll]

"intel couldn't have said that"

Dig Deep

Learn about some more key features of the Intel® Core™2 Duo desktop processor. Mention them to tech-saavy customers who demand detailed specs.

* Intel® Smart Cache - Outstanding performance, delivered.
Today, most processors are designed with one cache dedicated to one "execution core" But the Intel® Core™2 Duo processor was built without a dedicated cache for each execution core. So, each execution core shares the cache "intelligently" according to its needs. Having only one cache saves battery power and improves performance.

+

Intel® Advanced Smart Cache The shared L2 cache is dynamically allocated to each processor core based on workload. This efficient, dual-core optimized implementation increases the probability that each core can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.

This is the stuff they say about the cache in the C2Ds
They of course, WILL NOT say something bad about their OWN processor (i.e. they won't mention them by name)
One of the biggest boons to the C2D over the P4D was the fact that since the cache is unified, ALL the contents of the cache are available to both cores.
With the P4D, if core1 needed data for a request that was in the cache for core0, it'd have to be recached, if not already written.
the qx6700 is two c2d's in one package.
Conversely, it takes the P4D approach at achieving quad-thread. 2 nonlinked subpackages (core&cache)
The difference, is that each subpackage is dual core.
Think of the P4D955, that had HT enable-able.
It's the same thing, except instead of virtual 2nd and 4th cores, they are actual 2nd and 4th cores.
The QX6700 shines not in 4-way processsing on a single app, but on running 4 different apps at no performance hit. Because, it's not 4 unified cores.

However, the two men teams charge less combined than the four man team, and can start the job a year sooner.

Irrelevant to my question.

This efficient, dual-core optimized implementation

Notice how there isn't a quad-core optimized implementation?

The two teams of two would be working on one school, but they would occassionally have to negotiate through a third party to share each others' tools.

That is a better analogy. But, that example STILL shows how it would be less efficient. 4 workers who have all the tools they need, whenever they want them, versus two teams of two who have to wait on each other to share tools can't work as efficiently.

a QX6700 doesn't have an 8mb cache. It has 2 x 4mb caches. The content of the cache for cores 0 & 1 match the content of the cache for cores 2 & 3

I misspoke here. I meant to refer to the P4D.
In the P4D, the cache of core 0 and the cache of core 1 have to 'sync' up, and duplicate data if they are working together on a task. I'm not saying 100% duplication, but even 1% duplication of cache data is wasteful.
Intel IMPLIES when it speaks about the C2D that cached data needed by both cores only has to exist once. The graphic they used @ retailedge is now missing, but the illustration demonstrated how the blocks of data were being duplicated in an "old" dual core system, whereas they were not in a "new" core system

 

[coldpower27]

What's the benefit?

One of the big things that intel spouts about the superiority of the C2D platform over their OWN "P4D" is the fact that since there is a shared cache, the content of the cache doesn't have to be written twice.

a P4D @ 3.0GHZ x2mb cache doesn't have "4mb cache" it has 2mb cache, cause EVERY SINGLE damn thing gets written twice.

a QX6700 doesn't have an 8mb cache. It has 2 x 4mb caches. The content of the cache for cores 0 & 1 match the content of the cache for cores 2 & 3

Many tests show that, in some situations, the QX6700 underperforms it's dual core brother, the E6700. [most notably gaming, but multimedia in general]


If you don't understand why 4 cores working harmoniously together is superior to two teams of two, then I can't even begin to explain to you why I want to know when the product will be available.

Suns 8core design is nice, but not quite going to run the same hardware, o/s, applications as say a more mainstream product.


Yes, there is a low amount of available multithreaded apps, however, that doesn't mean they are non existent.

There is more waste in a "double dual" configuration than in a "true quad" configuration.

It may only be marginally better (whenever it is available) but, in the instances where quad core CAN be taken advantage of (think... these are the same instances where a 4 way processing solution such as that which is offered by the xeon / opteron (8xx) / itanium / etc...

a pair of dual socket computers working in tandem are not as efficient (depending on the app) as a single, 4 way processing system.

What I want to use it for is irrelevant. I want to know when it will exist, that was all.



You are building a simple, "one room school house" out of bricks,
You have FOUR masons working together. One mason per wall.

vs

You are building a pair of one room school houses.
2 masons per house.

Which school will be completed first? The 1 school being worked on by 4 men, or the 1 school being worked on by 2 men?

Yes, in double the time you'll have double the product, but, that still leaves the kids waiting to attend school, twice as long

I argue, that, the 4 masons working together could PROBABLY build an even BIGGER space before the two teams of two can get ONE done.




Why do I want it on a desktop solution? I don't like paying $1000 for my motherboards, then having to buy "special" ram, "Special" psus (n+1, eps) for my desktop computer.

A Shared Cache wouldn't have saved a Pentium D, there were other issues with the implementation of NetBurst, that made it not so desirable as a basis for a Dual Core Architecture.

The Shared Cache is only 1 of many improvements of Core 2 Duo in relation to Pentium D, unless both cores were working on the same set of data at the same time, then it isn't necessary to have duplicate sets of data in both cores.

In a Pentium D the 2x2MB implementation of Presler, would only be 2MB in Single Threaded Scenarios, though in MultiThreaded scenarios, it could reach the total 4MB if the 2 cores were working on different parts of the data at the same time. The only issue with a 2x2MB implementation is that they have to sync up once in awhile which requires communication through the FSB.

The Kentsfield implementation is a MCM and is a 2x4MB cache, however that doesn't mean all the data in Core 0/1 cache is duplicated in Core 2/3 cache, only in selected scenarios would duplication need to take place.

Depends in Multimedia encoding, if the program can take advantage of more cores, then QX6700 blows past the E6700 easily.

http://anandtech.com/cpuchipsets/showdoc.aspx?i=2866&p=14

Xmpeg 5.0.3 shows some substantial gains with Quad Core, as well as WME 9.

Your also complaining about a gaming performance disparity of typically 1-2 FPS on relatively high FPS already. Outside of gaming, I don't see where the QX6700 lags behind the E6700 in single threaded performance, because anything sufficiently multi threaded shows the advantages of the QX6700.

I suggest you stop utilizing subjective terminology, like "real" or "true" to describe what you are talking about.

What you want I believe, is a Quad Core processor, with inter-core communication happening between all 4 cores on the die itself without, leaving the die.

That doesn't look like it will happen for Intel till they move to Nehalem derivatives, I still believe Intel will package two 45nm dice together to create Yorkfield.

For AMD that will come in with their K8L/K10/Rev.H Altair/Agena though keep in mind even though AMD is coming in with a "native" (that's the term I utilize) Quad Core, there is no guarantee it will be superior to what Intel will be offering at that time. There are other factors that come into play when your comparing processors from 2 different corporations. The Native vs MCM issue, is just one of many factors which affect performance. For the desktop this is coming in sometime in Q3 2007.

Not necessarily a MCM implementation allows Intel to select two processors that have the same clockspeed potential to be put together, while a native Quad Core can only go as fast as it's slowest core, as well as allows easier inventory handling to address market needs, as they can build either Dual Core or Quad Core products, with a Native design your largely stuck building Quad Cores, you basically have to commit to that production.

Yes, we have already seen a slightly mild improvement from benching Opteron 2 Socket Single Core systems vs a Uni-Processors Opteron 1 Socket Dual Core system, it wasn't really enough of a difference to get excited over or anything though.

You will be able to buy the Kentsfield which is still a Quad Core processor for around 530 USD in Q2 2007, for 4 Cores at 2.4GHZ based on Core technology.

As well if I hadn't already explained, already prior in this post, what AMD is providing are 2 Dual Core Processors instead a Single Quad Core processor, as what defines a processor is what will fit into a Socket, and since Quad FX has 2 Sockets, it has 2 Processors, each with 2 cores for a total of 4.

 

[Klintus Fang]

+



This is the stuff they say about the cache in the C2Ds
They of course, WILL NOT say something bad about their OWN processor (i.e. they won't mention them by name)
One of the biggest boons to the C2D over the P4D was the fact that since the cache is unified, ALL the contents of the cache are available to both cores.

That much is true. But that is not what you said. You said that the non-unified cache has to write everything twice (once for each cache). It was that erroneous statement that I was responding to. And the quote from Intel does nothing to back up that original claim that you made.

Yes, it is true that a shared cache will do better for single threaded applications that might have a use for the larger cache in the case where the other cores are not using the cache. Ironically, that observation contradicts your original claim rather than supporting it. You were talking about the benefits of the cores sharing the cache while both are working together on the same problem. That case is the one case where the quote from Intel that you now are offering is not applicable. It has nothing to do with your claim that integrating the caches saves the core from having to "write everything twice". There is no such savings because the core doesn't have to write everything twice when the caches are split. While there is a benefit to sharing in that case where there is very heavy sharing between the cores, the problem with the argument you made on that point, is that desktop applications don't share data to a degree that matters.

In any case, the benefits of having the cores share that cache for desktop purposes is dubious. There is a reason, afterall, that the E6400 is such a popular processor over the E6600 amongst the people on these forums. It is because the 2MB cache that the E6400 uses is sufficient for most desktop purposes. The extra 2MB of cache that the E6600 provides is small for desktop applications. Now for this quad core case, you are talking about the difference between a 4MB and 8MB cache, which is an even smaller benefit. The benefits of increasing cache size hit diminishing returns very rapidly for all but the most esoteric of applications. For that reason, merging the two quad core caches into a single caches will have a very tiny impact on the single threaded performance so far as the increased effective cache size per-thread is concerned.

 

[chrisf6969]

FYI: when Intel goes native quad on 45nm its going to be 12Mb cache, not 8mb.

Sharing cache is effectively a "direct" communication between the cores, b/c they can both work on the same information in the cache with out having to go to the FSB.

 

[InorganicMatter]

When you ask? RIGHT NOW SAYS I:
http://www.newegg.com/Product/Produ...ntsfield&Submit=ENE&N=0&Ntk=all&Go.x=0&Go.y=0

 

[coldpower27]

FYI: when Intel goes native quad on 45nm its going to be 12Mb cache, not 8mb.

Sharing cache is effectively a "direct" communication between the cores, b/c they can both work on the same information in the cache with out having to go to the FSB.

The funny thing is that it's going to be a MCM module from the rumors I have been hearing it's not 12MB in the usual sense more like 2x6MB, as well from the rumors I have been hearing Bloomfield will have a 8MB cache for the 4 cores, but that is a Nehalem derivative.

 

[CyberDeus-RagDoll]

What you want I believe, is a Quad Core processor, with inter-core communication happening between all 4 cores on the die itself without, leaving the die.

I believe that is what I said in the very first post.

When will there be (in LGA775) a true, unified quad core solution? Do we have code names, road maps, etc to show this info?

Unified+Quad+Core

Not Unified Double Unified Dual Core

When you ask? RIGHT NOW SAYS I:
http://www.newegg.com/Product/Produ...ntsfield&Submit=ENE&N=0&Ntk=all&Go.x=0&Go.y=0

This would be an example of double dual. (2 @ 2=4)
not true quad. (4 @ 1=4)

 

[MrWizard6600]

jeez you guys, i did Ctrl+F and searched barcelona, nothing! I guess im the first to mention it! Gee I feel so special

Barcelona (and im NOT sure if im spelling that right) is AMDs native (in some respects) quad core CPU. it is one die, I dont know about the size of the bus between the cores but, I have seen a wafer w/ what is supposed to be barcilona. Heres the happy CEO now:

I think i got this one off Toms hardware, they did an artical stating that AMD has now a quad socket 16 cored server platform, centering around the chip you see on the left.

I hear rumers that it is allllmost ready to go but that it is a heat producing monster. It is apparently ready to be plugged into AMDs 4x4 platform. It is the begining of K8L. last I heard, its due Q2 or Q3 07. I saw this roadmap in october of 06.

As for the rest of the K8L lineup, the V--somethingorother dual core and the V--somethingorother single core procs, they are also part of the K8L line and they are said to be here Q3 or Q4 07. Im betting they're gonna give conroe a run for its money.

 

[coldpower27]

I believe that is what I said in the very first post.



Unified+Quad+Core

Not Unified Double Unified Dual Core




This would be an example of double dual. (2 @ 2=4)
not true quad. (4 @ 1=4)

Your using subjective terminology again, there is no such thing as a "true" or "real" Quad Core processor, what is out now are indeed very real Quad Core's. They are also very true Quad's. Double Die's are real Quad Core processors as long as they reamin on a Single socket.

There probably won't be Native Quad Core processors for LGA775 ever, Intel will move to a new Socket for Nehalem based processors which will have Native Quad Core units.

 

[coldpower27]

jeez you guys, i did Ctrl+F and searched barcilona, nothing! I guess im the first to mention it! Gee I feel so special

Barcilona (and im NOT sure if im spelling that right) is AMDs native (in some respects) quad core CPU. it is one die, I dont know about the size of the bus between the cores but, I have seen a wafer w/ what is supposed to be barcilona. Heres the happy CEO now:

I think i got this one off Toms hardware, they did an artical stating that AMD has now a quad socket 16 cored server platform, centering around the chip you see on the left.

I hear rumers that it is allllmost ready to go but that it is a heat producing monster. It is apparently ready to be plugged into AMDs 4x4 platform. It is the begining of K8L. last I heard, its due Q2 or Q3 07. I saw this roadmap in october of 06.

As for the rest of the K8L lineup, the V--somethingorother dual core and the V--somethingorother single core procs, they are also part of the K8L line and they are said to be here Q3 or Q4 07. Im betting they're gonna give conroe a run for its money.

Your spelling it wrong that is why, it's called Barcelona

 

[virtualrain]

Intel will move to monolithic quad core silicon as soon as yields (i.e. economics) allow... No sooner, no later. Simple as that. How long will that take... I would guess another 8-12 months.

 

[Scali2]

Now, there are some ways in which sharing the cache has a benefit.

1. if the threads running on the cores are really operating on the same data. In that case, and in only that case, will the data have to be stored in both caches. Unfortunately, even heavily multi-threaded server applications only share a small percentage of the actual data in the caches, and desktop and gaming applications share none of the data in the caches. So for gaming, this observation is irrelevant. And even for the server market, though it is sometimes relevant, and still doesn't automatically mean that sharing the cache is magically better. Even in that space, it will vary from application to application.

2. it reduces the cache-to-cache snoop traffic. snoop traffic is when the caches have to check each others contents for the purposes of keeping the data coherent. Whether or not that is an issue depends upon how the snoop protocol has been designed and at what level the snoops are managed, and on whether or not the FSB had enough bw to cover the extra FSB traffic that might occur. Do the snoops have to hop through the memory controller or is there a layer of logic on the die that manages coherency without having to go out to the memory controller? I don't actually know how the snoop protocol works for these chips so I can't answer that question. But I suspect that there is enough FSB bandwidth to handle it in either case if there are just two links to the memory controller, and that the issue is again only relevant to multi-threaded server apps that have heavy data sharing.

You are overlooking something here, I think...
That is that the shared cache is the same size as the non-shared cache... which means that in the worst case, both cores have completely different data, and effectively the cache per core is half that of the total shared cache.... So you are then pretty much even with the non-shared cache.
However, in many cases at least some of the data is shared, which means that the per-core cache size virtually grows. In the extreme case of a single-threaded application, the entire shared cache is used by one core, and therefore you have twice the cachesize as you would with a non-shared cache.
And games are exactly that type of application.

Also, your suspicions in 2. are not what I experienced when writing multithreaded code.
I noticed that sharing data between cores was about equal speed on an Athlon X2 and Pentium D... however, the Core2 Duo was considerably faster.
This meant that an algorithm where a second thread would actually be slower on X2 and P-D gave me a performance boost of over 20% on the C2D.
In other words, the shared cache allows for new types of optimizations. Code that would be slower on multiple cores/CPUs with non-shared cache (even with the hyped HTT-links), is now actually an improvement over the single-threaded code.

I have not run into a situation yet where the C2D scaled relatively worse than the X2 or the P-D yet, so I'm inclined to say that a shared-cache is a win-win situation... It's as fast or faster than non-shared cache when running regular multithreaded code, or multiple processes... and it allows for new ways to optimize code.

 

[MrWizard6600]

Your spelling it wrong that is why, it's called Barcelona

couldnt even find bar or ber. no ones mentioned it!

I'm still

 

[coldpower27]

couldnt even find bar or ber. no ones mentioned it!

I'm still

Whatever makes you sleep better at night. There have been several instances of use of the word Barcelona on HardForum's. It also helps if you know how to search, and limit your search to the AMD forums and use display as posts instead of threads to help reduce the clutter.

Just because you couldn't find it doesn't mean it doesn't exist.

 

[CyberDeus-RagDoll]

FWIW, guys...

I actually found a half answer to my question

They Yorkfield core will be the first 4 core on 1 die in one package (instead of 2 cores on 2 dies in one package that is the case with kentsfield)

The Yorkfield will have 8 MiB of fully shared L2 cache (the Kentsfield has two separate 4 MiB L2 caches, shared separately by each pair of processors).

 

[MrWizard6600]

Whatever makes you sleep better at night. There have been several instances of use of the word Barcelona on HardForum's. It also helps if you know how to search, and limit your search to the AMD forums and use display as posts instead of threads to help reduce the clutter.

Just because you couldn't find it doesn't mean it doesn't exist.

ctrl + f on this page, and page 1

my point is no one in this thread has mentioned the proc.