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Question on thread X6 thread bouncing

zentech1

n00b
Joined
Mar 8, 2005
Messages
36
I don't have an X6 yet but have a question. I currently have a Phenom I (9950BE) and with windows Vista and Windows 7 I have an issue when using C'n'Q that windows continually moves the threads around to different cores so that the lower clocked cores speed up, and then back down as the threads continually bounce. THis is just how a Phenom I works, it independently can adjust core speed with C'n'Q. With Phenom II the problem is fixed because all cores share the same speed (i think), so if ones sped up they all speed up, and even though the threads bounce still, they are not bouncing to lower speed cores. Ok finally my X6 question.. How does turbo ever work, because would Windows also just bounce the threads around to every core on the X6, thus never letting any of the cores stay throttled? I know its not C'n'Q, but wouldn't turbo also be affected by thread bouncing?
Thanks!
 
not sure exactly what you mean(just got back from graduation, too tired to read), but with Turbo core the last three cores are shot down to ~800 MHz, and the first three are shot up to whatever the Turbo Core value is for your chosen chip....everyonce and a while ill see Core 0 drop in speed(for seconds) then jump to normal....
 
Windows likes to just randomly throw threads around to different cores randomly. I am trying to figure out what keeps the active threads on the 3 cores that are boosted up. From what I have seen of windows, including Win7, it will take a thread and just move it randomly, even to a core that is running at a slower speed. Is this the same with the X6 and turbo, will windows keep moving threads running on the 3 boosted cores to the unboosted cores, thus causing those cores to boost and the orginal boosted cores to slow down, in a repeating cycle? Sorry if I am not being clear.

Thanks.
 
naw, your being perfectly clear, im just dead tired(not sure why I havent fallen asleep...maybe waiting for the hottub lol), anyhow, from what I understand Turbo is enabled on three active cores, when three others have little/no use....I havent seen it come up because i have my chip doing BOINC whenever im not actually using it, so all cores are typically between 80-100% usage for me....i would think that as a core is used, and one goes "Off the grid" the turbo speeds change, but something is nagging at me from the back of my head saying that only the first three cores will jump up in speed
 
Thanks for the replies. Im planning on picking an X6 up, just waiting for the bios to drop for my mb, Asus M3A79-T Deluxe. Seems to be taking awhile.
Thanks again.
 
I don't have an X6 yet but have a question. I currently have a Phenom I (9950BE) and with windows Vista and Windows 7 I have an issue when using C'n'Q that windows continually moves the threads around to different cores so that the lower clocked cores speed up, and then back down as the threads continually bounce. THis is just how a Phenom I works, it independently can adjust core speed with C'n'Q. With Phenom II the problem is fixed because all cores share the same speed (i think), so if ones sped up they all speed up, and even though the threads bounce still, they are not bouncing to lower speed cores. Ok finally my X6 question.. How does turbo ever work, because would Windows also just bounce the threads around to every core on the X6, thus never letting any of the cores stay throttled? I know its not C'n'Q, but wouldn't turbo also be affected by thread bouncing?
Thanks!


as long as you only have half the cores under load windows will leave it on those 3 cores.. so for example with my x4 940.. if i load up 2 cores.. only core 0 and 1 stay under load.. if i load up 3 cores.. core 0 and 1 stay under full load but core 2 and core 3 share the extra load.. so in the case of the x6's.. no matter what core 0 1 and 3 will stay under load thus triggering the turbo mode but once you load up 4 cores it will share the load of that 4th core over core 3 4 and 5.. its just the way AMD has designed the processors work and share the load over cores.. so basically 0 1 2 are shared and 3 4 and 5 are shared.. hopefully that makes sense..
 
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