Question about understanding data flow.

[ThirtySixBelow]

I'm trying to learn more about motherboards, so I was reading about the northbridge and southbridge. The northbridge seems to be a the central location, or traffic cop, for data going to the ram and cpu and agp/pci busses. I'm curious about how this works. I'll use a conroe chip and dual channel DDR2 533 ram in my scenario for understanding what is going on. If the CPU gets a request to put something in ram and the fsb is 266mhz, how does it make this transition? Are their 4 pipes for the data to go out in one clock cycle since the conroe is 1066mhz and the bus can only go at 266mhz? Does each stick of ram have 2 pipes going to the northbridge? Am I close, or way off?

Also with AMD having their memory controllers on the chip, does this flow just skip over the northbridge all together (having a direct route) for RAM to CPU communication? Does the flows principle remain the same, just that it's not using the northbridge as it's "traffic cop" because it is on the chip?

 

[metallicafan]

Well I'll try to take a stab at this one, someone correct me if I'm wrong.

If the CPU gets a request to put something in ram and the fsb is 266mhz, how does it make this transition? Are their 4 pipes for the data to go out in one clock cycle since the conroe is 1066mhz and the bus can only go at 266mhz? Does each stick of ram have 2 pipes going to the northbridge?

There are not "data pipes" in the way you are assuming. There is one data bus that goes from the CPU to the Northbridge and then that bus continues to the RAM. This bus is like 64 bits or 128 bits wide ( I forget which it is ). Since the Intel motherboards use a system clock of 266Mhz, it has to send 4 bits/clock cycle to achieve a FSB clock of 1066.

The Northbridge is indeed a trafic cop but its a trafic cop for lots of things. In Intel systems it not only takes read and write requests to the RAM but also sends commands to the other system components like AGP slots, PCI slots, etc.

Also with AMD having their memory controllers on the chip, does this flow just skip over the northbridge all together (having a direct route) for RAM to CPU communication? Does the flows principle remain the same, just that it's not using the northbridge as it's "traffic cop" because it is on the chip?

Yeah for CPU to RAM communications AMD CPUs have direct access to the RAM and do not have to go through the Northbridge, however communication with other system components, like a PCI slot, go through the Northbridge.

 

[ThirtySixBelow]

There are not "data pipes" in the way you are assuming. There is one data bus that goes from the CPU to the Northbridge and then that bus continues to the RAM. This bus is like 64 bits or 128 bits wide ( I forget which it is ). Since the Intel motherboards use a system clock of 266Mhz, it has to send 4 bits/clock cycle to achieve a FSB clock of 1066.

If it's 64/128 bits wide, why is it sending 4 bits/clock?