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Prescott Celeron acctually GOOD!?!?!?

Juan Sanchez

Limp Gawd
Joined
Oct 31, 2003
Messages
369
I found this article (in french) about the new Prescott based Celeron. Well I was shocked and amazed that the chip performed very nicely. Throught the test it was only slightly behind the Pentium 4 at the same speed. At the end it notes that it was capable of being OC'ed to 3.2 Ghz. FINALLY a good Celeron again!!!!






oh........heres the link

http://www.x86-secret.com/popups/articleswindow.php?id=101
 
Definately an improvement, but im still quite pessimistic about how it's performance is gonna scale with clockspeed.
 
Interesting to see a celeron with half the cache take out a 2.4b in some tests. If pricing is right (sub $90) this could potentially be a killer chip in the budget sector.
 
About time :)

Looking at the graphs, it performs roughly around where an old williamette would at the same speed/FSB, give or take 5% due to the longer pipeline and cache assoiativity.

Looks like an interesting CPU, it should be much better competition for the Athlon XPs, especially if the price is no more than $100.
 
So many apps are optimized for 256KB L2 since thats what most processors have, even back to the P2, P3, etc. (some had 512, off die, etc) But 256KB is really the bare minimum anything less it performance drops off in A LOT of apps.
 
Originally posted by acascianelli
too bad theres no hack to enable HT

grah I was going to ask that

its not worth my money then. if it had HT id definitly consider it
 
I want intel to make a damn chip like the athlon..

I so wish I could RMA my 2.4b :(.

Damn 7 day processor RMA RULE!
 
I may very well get one of the Prescott based Celerons for a HTPC when they come out...
 
Originally posted by MemoryInAGarden
It's a cheap way to replace the Willy.
That's what she said :D

Sorry, lame attempt at a double-entendre.....

This chip shows promise, and if this is indicative of the final silicon, it seems Intel is following the Celeron trend... i.e., very first cachless Celery sucked, 300A was the must have. Celery CuMine wasn't too good, Tualeron kicked ass. P4-Celery sucked worse than any Celeron equivalent ever conceived. Now this little guy... I wonder how Intel will fumble up the consequent Celeron after Celercott.
 
Originally posted by PliotronX
That's what she said :D

Sorry, lame attempt at a double-entendre.....

This chip shows promise, and if this is indicative of the final silicon, it seems Intel is following the Celeron trend... i.e., very first cachless Celery sucked, 300A was the must have. Celery CuMine wasn't too good, Tualeron kicked ass. P4-Celery sucked worse than any Celeron equivalent ever conceived. Now this little guy... I wonder how Intel will fumble up the consequent Celeron after Celercott.

make it not have HT even though theres no reason it wouldnt? OOPS!
 
HT is very cache dependent, this chip would suffer badly if HT was enabled. (remember the first xeons with ht)
 
Originally posted by Merlin45
HT is very cache dependent, this chip would suffer badly if HT was enabled. (remember the first xeons with ht)

By the time intel release a revised Celeron all Pentium cpu's will have 1mb (or more) for sure. 512k will be nothing at that point.
 
And A64 chips already have 1MB cache; although i don't see why they need that much. The difference in performace between an A64 3000+ and a 3200+ is within 4% on average, and the only difference is the 3000+ has 512k cache, as the latter has 1Mb.
 
Cache is something that is easy to add on in terms of complexity, but quickly reaches the point of diminishing returns. Desktop chips don't really need all that much given the working sets of the programs commonly run, much less the overall number being run at once. If you're in a server and much more I/O intense environment, that extra cache matters a lot. It certainly doesn't help much that cache uses up an abhorrent amount of die space.
 
Cache = very expensive static ram. If you were to replace all your ram with static ram, it would costs you thousands, but it would run synchronous with the CPU for uber high speeds and virtually no latency at all.
 
on die cache = virtually no latency - makes things FASTER

It helps alleviate the slow downs from having to go to system ram. The reason why on the A64 there's not as big of a difference from 512 to 1Mb is 2 reasons

#1 - integrated memory controller already reduces latency of going to system ram greatly (VIP)

#2 - 512Mb is usually enough and when its not like games, etc... they have to go to system memory constantly for either 512 or 1Mb.
 
There are no limits on how big you make the die (theoretically). You can make it bigass and put a gig of cache on it, to replace the ram completely, also, in theory.
 
Originally posted by M4d-K10wN
There are no limits on how big you make the die (theoretically). You can make it bigass and put a gig of cache on it, to replace the ram completely, also, in theory.

Heh try cooling it though...

Cache = very expensive static ram. If you were to replace all your ram with static ram, it would costs you thousands, but it would run synchronous with the CPU for uber high speeds and virtually no latency at all.

Wouldnt make much of a difference with the memory controllers of today. Even opteron/FX on-die dual channel controller wouldn't be sufficient with a static type memory as system ram.
 
If you ran it syncronous with the processor it would make a huge difference, that is a 3.4 ghz memory bus for the fastest procs.
 
Originally posted by Merlin45
If you ran it syncronous with the processor it would make a huge difference, that is a 3.4 ghz memory bus for the fastest procs.

What I said.... is that if there was system memory available like described, it would be almost of no use right now with the current memory controllers limitations.

Obviously syncronized memory would be extremely fast.
 
but what he said was that if you used static ram, you would run it syncronised, that would be the point of using static ram.
 
Originally posted by Merlin45
but what he said was that if you used static ram, you would run it syncronised, that would be the point of using static ram.

Sigh...

Static ram would be great. Its possible to create memory like this as the technology is there. The technology is not there for northbridge chipsets or on-die memory controllers. You would not be able to impliment this type of ram until chipset makers made a memory controller that could handle syncronized system memory. Until them we are stuck with DDR. Take the 875 chipset for example. If you were to somehow get it to run memory at 3600Mhz (cpu multi 1 x 3600FSB with no latency) I think the chipset would be glowing orange from heat. That is if you could get it to magicly run past its 3xxmhz barrier.
 
SRAM also nukes you with extreme price :(. Well, if you're going to put the whole thing on the Die, the CPU, the ram, and all, you might as well shove a north and south bridge in there.
 
why would you need a chipset memory controller? if the memory was running syncronously and it was static ram (just like the caches) then the cpu could handle it itself. (after all, it is essentially a really big cache off chip).
 
Although in the enthusiast crowd, the AthlonXP 2400+M might still be a better performer, the case isn't the same in the budget pc market Intel is aiming for. This seems to be a reasonable chip and with the Prescott's better branch prediction, apparently the cache loss does not nearly show as huge a loss in performance as was apparent with the Northwoods. Intel has no problem marketing the Celeron, and now, it actually performs decently well - possibly a revival to the old Celeron days?
 
Theorycraft rules ;). You would need an on-die NB for addressing the video card, and everything else on the bus though. And without some sort of a buffer, any OS would handle the huge cache as regular cache, and it won't use most of it, while if it has a memory controller, even one that does nothing whatsoever, you could still have all the goodness of SRAM, and it would handle it as regular ram, i suppose. You could also set if for 0 latency, assuming your controller is a 'dummy'.
 
You'd think the Prescott Celerons would be rather bad processors... deep pipelined processors love more cache, but it seems the double cache helps more than the deeper pipeline damages.

A gig of static on-die memory would cost a fortune. :p

No, actually, it would cost several fortunes.
 
The new celeron doesn't seem that much better than the old one. Its taken steps closer, probably due to the increased FSB (bandwidth jumps were always huge for performance) but its still at best tying with the new cut down prescott and 400FSB Northwood, and at worst, its slower than even the old Celeron. The overclocking is about the same that people saw with the old celerons so thats not much improved either.
 
Originally posted by Koz
The new celeron doesn't seem that much better than the old one. Its taken steps closer, probably due to the increased FSB (bandwidth jumps were always huge for performance) but its still at best tying with the new cut down prescott and 400FSB Northwood, and at worst, its slower than even the old Celeron. The overclocking is about the same that people saw with the old celerons so thats not much improved either.

New Prescott Celerons coming out will have a 533FSB.
 
Originally posted by Koz
The new celeron doesn't seem that much better than the old one. Its taken steps closer, probably due to the increased FSB (bandwidth jumps were always huge for performance) but its still at best tying with the new cut down prescott and 400FSB Northwood, and at worst, its slower than even the old Celeron. The overclocking is about the same that people saw with the old celerons so thats not much improved either.

Why would it be slower than current Celerons?
 
Because it is still based on the Prescott core. Tests in which the Northwood strongly beat Prescott would probably also have the Northwood Celeron beating the Prescott Celeron. In the benches there was at least one test that had these results. I do think that this is a step in the right direction however, I think it may need another cache jump to really become a stellar budget performer because of the lengthened pipeline.
 
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